Digital drive system for pulse width modulated power control

Claim 2

A digital drive system for pulse width modulated power control including an output transformer (25), power amplifier means (21, 23) for driving said output transformer (25), load means connected to receive an a.c. output signal from said transformer (25), characterized in that the drive system for said power amplifier means comprises first and second flip-flop circuits (20, 22) connected to said power amplifier means (21, 23), gate means, connected to said flip-flop circuits (18), a presettable up/down counter (14) connected to said gate means, said counter including "CARRY" and "BORROW" input lines from said counter (14) to said gate means (18), digital means (10) containing a digital number defining the desired amplitude of the next cycle of said power amplifier means (21, 23) connected to provide an input signal to said presettable up/down counter (14), a clock connected to said presettable up/down counter (14) providing output pulses at a frequency greater than the desired output frequency of said system by a desired multiple, counter means connected to said clock including a first divider (24) for dividing said clock output by a first factor of said multiple and a second divider (26) dividing said first divider (24) output by two and having a second output wherein said first divider output is divided by four, means connecting said first output to an up/down terminal of said presettable up/down counter (14) and to the "D" terminals of said flip-flops (20, 22), means connecting the second output of said second divider to the reset terminal of said first flip-flop (20), means connecting the inverse of the second output of said second divider to the reset terminal of said second flip-flop (22), a third output (16) of said second divider operative when both of said first and second outputs of said second divider (26) are true serving as a preset load command to the presettable up/down counter (14) connecting the digital number in said digital register to said presettable up/down counter (14) whereby upon receipt of said command said presettable up/down counter (14) will count clock pulses until the count of said presettable up/down counter (1 4 ) overflows, causing said presettable up/down counter (14) to generate a carry pulse to said gate means (18) thereby causing said first flip-flop (20) output to change state, means responsive to a change of state of said first output of said second divider to cause said presettable up/down counter (14) to count down the counts representing said digital number at which time it generates a borrow count causing first flip-flop (20) to return to its original state, following which said presettable up/down counter (14) continues to count down until said second divider (26) first output again changes state and said second output of said divider (26) also changes state resulting in inhibiting said first flip-flop (20) and enabling said second flip-flop (22) to cause a repetition of the above cycle for said second flip-flop (22), said system continuing to repeat said cycles for a desired period of time.

Claim 3

A digital drive system as claimed in Claim 1 wherein said power amplifier means includes a pair of field effect transistors (96, 106), one connected to the output of each of said flip-flops and each of said field effect transistors (96, 106) is connected to one half of the primary winding of said output transformer (112), a center tap of said primary winding being connected to a source of direct current voltage.

Claim 4

A digital drive system as claimed in Claim 2 wherein a high frequency spike suppression circuit is connected between the drain and source terminals of each of said field effect transistors (102, 104), said spike suppression circuit including a resistor and a capacitor in series.

Claim 5

A digital drive system as claimed in Claim 2 wherein a circuit for suppressing high voltage spikes connected between the ends of said primary winding ground, said circuit including a capacitor (128' third field effect transistor (118) with a re (117) connected in series across said capacitor, a plurality of series connected zener diodes (120, 122, 124) having a breakdown voltage higher than twice the voltage of said direct current voltage source but lower than that which would damage said first and second field effect transistors (96, 106) connected across the gate to drain junction of said third field effect transistor (118), a fourth zener diode (126) connected across the gate to source junction of said third field effect transistor (118), and resistance means (130) having a high value connected across said plurality of zener diodes as a means of discharging said capacitor (128) when power is removed from said system.

Claim 6

A digital drive system as claimed in Claim 2 wherein a zener diode (94, 98) is connected in the input circuit of each of said field effect transistors (96, 106) to protect said transistors (96, 106) against voltage spikes or surges exceeding the desired input voltage.

Claim 7

A digital drive system as claimed in Claim 1 wherein said digital means containing a digital number (44) is connected to an amplitude data source (46) and means are provided for clocking said amplitude data into said digital means (44).

Claim 8

A digital drive system as claimed in Claim 1 wherein a digital phase data register (132) is connected to said second divider (38), phase data means (134) are connected to said phase data register and a phase clock (136) is provided for clocking phase data into said phase data register (132) for varying the output phase of said system relative to said first named clock.

Claim 9

A digital drive system as claimed in Claim 1 wherein the amplitude information is stored in a counter (44) which is incremented or decremented in response to an error signal representing the departure of the output voltage from a desired value.

Claim 10

A digital drive system as claimed in Claim 1 wherein a third flip-flop (66) is connected to a first line (70) carrying a safety lock out signal and a second terminals of said first (176) and second (178) flip-flops, a third divider (150) is provided essentially identical to said second divider (148) having its first output connected to the up/down terminal of said second presettable up/down counter (144) and to the "D" terminals of said third (180) and fourth (182) flip-flops, a fourth divider (152) is provided essentially identical to said second divider (148) having its first output connected to the up/down terminal of said third presettable up/down counter (146) and to the "D" terminals of said fifth (184) and sixth (186) flip-flops, means are provided connecting the second output of said third divider (150) and of said fourth divider (152) to the reset terminals of said third (180) and fifth (184) flip-flops, respectively, means are provided connecting the inverse of the second output of said third (150) and fourth (152) dividers to the reset terminals of said fourth (182) and sixth (186) flip-flops, respectively; a third output of each of said third (150) and fourth (152) dividers operative when both of the first and second outputs of said third (150) and fourth (152) dividers are true serving as a preset load command to the second (144) and third (146) presettable up/down counters, respectively, to connect the digital number in said digital register to said second (144) and third (146) presettable up/down counters to cause said counters (144, 146) to count clock pulses in the same manner as said first named presettable up/down counter (142), first (154), second (156) and third (158) digital phase data registers connected to said second (148), third (150) and fourth (152) dividers, phase data means connected to said phase data registers (154, 156, 158) which data calls for said phases to differ by 120 degrees, and phase clock means (140) for clocking said data into said phase data registers. line (68) carrying a turn on signal, said flip-flop (66) being connected to a gate circuit (74), an inverter connected to said first line (70) and to said gate circuit (74) said gate circuit (74) having its output connected to said first (34) and second (38) dividers to cause said dividers to stop, and means (50) connecting said preset load command to said third flip-flop (66) such that said gate circuit (74) is not caused to stop said dividers (34, 38) until a load command pulse is received indicating the completion of a full output cycle.

Claim 11

1 0 . A digital drive system as claimed in Claim 1 wherein said load means is a three-phase load device (208) having three load windings, said power amplifier means including first (202), second (204) and third (206) amplifiers driving each of said load windings, said first (176) and second (178) flip-flop circuits are connected to said first amplifier (202), third (180) and fourth (182) flip-flop circuits are provided connected to said second amplifier (204), fifth (184) and sixth (186) flip-flop circuits are provided connected to said third amplifier (206), said gate means includes a first gate circuit (170) connected to said first (176) and second (178) flip-flops, a second gate circuit (172) connected to said third (180) and fourth (182) flip-flops, and a third gate circuit (174) connected to said fifth (184) and sixth (186) flip-flops, said presettable up/down counter (142) is connected to said first gate circuit (170) and a second presettable up/down counter (144) is provided connected to said second gate circuit (172) and a third presettable up/down counter (146) is provided connected to said third gate circuit (174), said digital means containing a digital number (166) is connected (168) to provide identical amplitude information to said first (142), second (144), and third (146) presettable up/down counters, said second divider (148) has its first output connected to the up/down terminal of said first presettable up/down counter (142) and to the "D" terminals of said first (176) and second (178) flip-flops, a third divider (150) is provided essentially identical to said second divider (148) having its first output connected to the up/down terminal of said second presettable up/down counter (144) and to the "D" terminals of said third (180) and fourth (182) flip-flops, a fourth divider (152) is provided essentially identical to said second divider (148) having its first output connected to the up/down terminal of said third presettable up/down counter (146) and to the "D" terminals of said fifth (184) and sixth (186) flip-flops, means are provided connecting the second output of said third divider (150) and of said fourth divider (152) to the reset terminals of said third (180) and fifth (184) flip-flops, respectively, means are provided connecting the inverse of the second output of said third (150) and fourth (152) dividers to the reset terminals of said fourth (182) and sixth (186) flip-flops, respectively; a third output of each of said third (150) and fourth (152) dividers operative when both of the first and second outputs of said third (150) and fourth (152) dividers are true serving as a preset load command to the second (144) and third (146) presettable up/down counters, respectively, to connect the digital number in said digital register to said second (144) and third (146) presettable up/down counters to cause said counters (144, 146) to count clock pulses in the same manner as said first named presettable up/down counter (142), first (154), second (156) and third (158) digital phase data registers connected to said second (148), third (150) and fourth (152) dividers, phase data means connected to said phase data registers (154, 156, 158) which data calls for said phases to differ by 120 degrees, and phase clock means (140) for clocking said data into said phase data registers.