Integrated circuit for checking boundaries

Claim 2

Digital single-chip integrated circuit bounds checker means responsive to a first plural-bit numeric data word ("data-to-be-compared") for receiving and storing a second and a third plural-bit numeric data word ("lower-" and "upper-limits", respectively,) and for generating at a first output a signal indicative of whether said data-word-to-be-compared bears a first selectable numeric relationship to said lower-limit data word, at a second output a signal indicative of whether said data-word-to-be-compared bears a second selectable numeric relationship to said upper-limit data word, and at a third output a signal indicative of whether said data-word-to-be-compared bears a third selectable numeric relationship to said lower- and upper-limit data words.

Claim 3

Bounds checker means according to claim 1 comprising first and second register means for receiving said lower- and upper-limit data words, respectively, and for temporarily storing said data words, first and second comparator means connected to said first, said second, register means, respectively, responsive to said data-word-to-be-compared, for generating at a first, respectively, a second comparator means output, said signal indicative of said first, respectively, said second, selectable relationship, said first, respectively, said second output of said comparator means forming said first, respectively, said second, output of said bounds checker means, and gate means connected to said outputs of said first and said second comparator means for generating at an output said signal indicative of said third selectable relationship, said gate means output forming said third output of said bounds checker means.

Claim 4

Bounds checker means according to claim 2 further including an input data bus connected to said first and second register means and to said first and second comparator means, wherein said first, respectively, said second register means, is responsive to a first, respectively, second, load register signal whereby a plural-bit data word can be conducted via said input data bus to said first and said second comparator means, and whereby, a plural-bit data word can be conducted via said input data bus to said first register means, said second register means, and stored therein upon application of a HIGH said first, respectively, said second, load register signal.

Claim 5

Bounds checker means according to claim 2 wherein said first, respectively, said second comparator means, is responsive to a first, respectively, second, carry-in signal, whereby said output of said comparators and said gate corresponding to said first and second, said third, respectively, selectable numeric relationship is greater-than or greater-than-or-equal-to, less-than or less-than-or-equal to, outside the-open- interval or outside the-open-left-closed-right-interval or outside the-closed-left-open-right-interval or outside the-closed-interval, respectively, depending on whether said first carry-in signal is a LOW or a HIGH, said second carry-in signal is a LOW or a HIGH, said first and said second carry-in signals are a LOW or said first carry-in signal is a LOW and said second carry-in signal is a HIGH or said first carry-in signal is a HIGH and said second carry-in signal is a LOW, or said first and said second carry-in signals are a HIGH, respectively.

Claim 6

Bounds checker means according to claim 2, wherein said first, second and third numeric data words can be in either unsigned or signed two's complement notation, and wherein said comparator means are responsive to a signed-number signal, whereby said output of said comparator means and said gate means corresponding to said selectable numeric relationship is generated for either said unsigned, or said signed, respectively, numeric data words, depending on whether said signed-number signal is a LOW, or a HIGH, respectively, in a manner which imposes no added gate delay compared to the time required by said bounds checker means capable of operating only on either said unsigned or said two's complement notation data words, exclusively.

Claim 7

Bounds checker means according to claim 5 wherein said first, respectively, said second comparator means comprises a first, respectively, a second, plurality of low-order logic cell means receiving true, respectively, complemented signals representing predetermined low-order bit positions of said plural-bit data-word-to-be-compared, and complemented, respectively, true, signals representing predetermined low-order bit position of said plural-bit data word stored in said first, respectively, said second, register means for generating low-order generate (GEN . ) and low-order propagate (PROP . ) signals therefrom, a first, respectively, a second high-order logic cell means receiving a true and a complemented signal representing the high-order bit position of said plural-bit data word-to-be-compared and a true and a complemented signal representing the high-order bit position of said plural-bit data word stored in said first, respectively, said second register means, and receiving said signed-number signal for generating a high-order unsigned/signed generate (GEN ) signal and a high-order unsigned/signed propagate (PROP) signal therefrom, and a first, respectively, a second lookahead carry logic means receiving said low-order generate and propagate signals and said high-order unsigned/signed generate and propagate signals, generated by said first, respectively, said second logic cells, and receiving said first, respectively, said second, carry-in signal, for generating, therefrom said signals formed at said comparator means output, wherein said first plurality of low-order logic cell means perform the following logical operations on the signals representing the complement of the bit position of said data word stored in said first register means (L i ) and the bit position of said data word-to-be-compared (D i ): wherein said first high-order logic cell means performs the following logical operations on the signals representing the high-order true and complemented bit position of said data-word-to-be-compared (D , D n ) and the n high-order true and complemented bit position of said data word stored in said first register means, (L , L n ); if signed-number signal is HIGH if signed-number signal is LOW if signed-number signal is HIGH if signed-number signal is LOW, wherein said second plurality of low-order logic cell means perform the following logical operations on the signals representing the complement of the bit position of said data-word-to-be-compared ( D i ) and the bit position of said data word stored in said second register means (U i ): and wherein said second high-order logic cell means performs the following logical operations on the signals representing the high-order true and complemented bit position of said data-word-to-be-compared (D , D n ) and the high-order true and complemented bit position of said data word stored in said second register means ( U n' U n ); if signed-number signal is a HIGH if signed-number signal is a LOW if signed-number signal is a HIGH if signed-number signal is a LOW, whereby, said first comparator means performs a subtraction of said data word stored in said first register means from said data-word-to-be-compared using said first carry-in signal as the input to the least significant bit position to said first lookahead-carry logic means, a HIGH output signal thereof indicative of said first numeric relationship that said data word stored in said first register means is less than, respectively, less-than-or-equal-to, said data-word-to-be-compared, if said first carry-in signal is a LOW, respectively a HIGH, a LOW output signal thereof indicative of said first numeric relationship that said data word stored in said first register means is greater-than-or-equal-to, respectively, greater-than, said data-word-to-be-compared, if said first carry-in signal is a LOW, respectively, a HIGH, and whereby, said second comparator means performs a subtraction of said data-word-to-be-compared from said data word stored in said second register means using said second carry-in signal as the input to the least-significant bit position to said second lookahead carry logic means, a HIGH output signal thereof indicative of said second numeric relationship that said data word stored in said second register means is greater-than-or-equal-to, respectively, greater than, said data-word-to-be-compared, if said second carry-in signal is a HIGH, respectively, a LOW, a LOW output signal thereof indicative of said second numeric relationship that said data word stored in said second register means is less-than, respectively, less-than-or-equal-to, said data-word-to-be-compared, if said second carry-in signal is a HIGH, respectively, a LOW.

Claim 8

Digital single-chip integrated circuit bounds checker means which operates on first, second and third unsigned or signed two's complement notation numeric data words responsive to said first plural-bit numeric data word ("data-to-be-compared") and a signed-number signal for receiving and storing said second and said third plural-bit numeric data word ("lower-" and "upper-limits," respectively) and for generating at a first output a signal indicative of whether said data-word-to-be-compared bears a first selectable relationship to said lower-limit data word, at a second output a signal indicative of whether said data-word-to-be-compared bears a second selectable numeric relationship to said upper limit data word, and at a third output a signal indicative of whether said data-word-to-be-compared bears a third selectable numeric relationship to said lower- and upper-limit data words, comprising: an input data bus; first and second register means connected to said input data bus, responsive to a first, respectively, a second, load register signal for receiving said lower-, respectively, said upper-limit data words conducted thereto via said bus and for temporarily storing said data words in response to said load register signals; a first and second plurality of low-order logic cell means connected to said input data bus and connected to said first, said second, register means, respectively, responsive to said data-word-to-be-compared conducted thereto via said bus, each said first low-order logic cell means, respectively, each said second low-order logic cell means, receiving true signals representing predetermined low-order bit positions of said plural-bit data-word-to-be-compared and signals representing predetermined low-order bit positions of said plural-bit data word stored in said first, said second, register means, respectively, for generating low-order generate (GEN i ) and low-order propagate (PROP i ) signals therefrom; a first and a second high-order logic cell means connected to said input data bus and connected to said first, said second, register means, respectively, responsive to said data-word-to-be-compared conducted thereto via said bus, said first high-order logic cell means, respectively, said second high-order logic cell means, receiving a true and a complemented signal representing the high-order bit position of said plural-bit data-word-to-be-compared and a signal representing the high-order bit position of said plural-bit data word stored in said first, said second, register means, respectively, and receiving said signed-number signal for generating a high-order unsigned/signed generate (GEN ) signal and a high-order unsigned/signed propagate (PROP) signal therefrom; a first and a second lookahead carry logic means receiving said low-order generate and propagate signals and said high-order unsigned/signed generate and propagate signals, for generating therefrom at said first, respectively, said second, output of said bounds checker means, said signal indicative of said first, respectively, said second, selectable relationship; and gate means connected to said first and said second lookahead carry logic means receiving said signals indicative of said first and said second selectable relationships, for generating therefrom at said third output of said bounds checker means said signal indicative of said third selectable relationship; whereby said lower-, respectively upper-limit, plural-bit data word can be conducted via said input data bus to said first register means, respectively, said second register means, and stored therein upon application of a HIGH said first, respectively, said second, load register signal;and whereby said signals formed on said first, second and third outputs of said bounds checker means corresponding to said selectable numeric relationship is generated for either said unsigned, or said signed, respectively, numeric data words depending on whether said signed-number signal is a LOW, or a HIGH, respectively, in a manner which imposes no added time delay compared to the time required by said bounds checker means capable of operating only on either said unsigned or said two's complement notation data words, exclusively.

Claim 9

Digital single-chip integrated circuit bounds checker means which operates on first, second and third unsigned or signed two's complement notation numeric data words responsive to said first plural-bit numeric data word ("data-to-be-compared") and a signed-number signal for receiving and storing said second and said third plural-bit numeric data word ("lower-" and "upper-limits," respectively) and for generating at a first output a signal indicative of whether said data-word-to-be-compared bears a first selectable relationship to said lower-limit data word, at a second output a signal indicative of whether said data-word-to-be-compared bears a second selectable numeric relationship to said upper limit data word, and at a third output a signal indicative of whether said data-word-to-be-compared bears a third selectable numeric relationship to said lower- and upper-limit data words, comprising: an input data bus; first and second register means connected to said input data bus, responsive to a first, respectively, a second, load register signal for receiving said lower-, respectively, said upper-limit data words conducted thereto via said bus and for temporarily storing said data words in response to said load register signals; a first and second plurality of low-order logic cell means connected to said input data bus and connected to said first, said second, register means, respectively, responsive to said data-word-to-be-compared conducted thereto via said bus, each said first low-order logic cell means, respectively, each said second low-order logic cell means, receiving true signals representing predetermined low-order bit positions of said plural-bit data-word-to-be-compared and signals representing predetermined low-order bit positions of said plural-bit data word stored in said first, said second, register means, respectively, for generating low-order generate (GEN i ) and low-order propagate (PROP i ) signals therefrom; a first and a second high-order logic cell means connected to said input data bus and connected to said first, said second, register means, respectively, responsive to said data-word-to-be-compared conducted thereto via said bus, said first high-order logic cell means, respectively, said second high-order logic cell means, receiving a true and a complemented signal representing the high-order bit position of said plural-bit data-word-to-be-compared and a signal representing the high-order bit position of said plural-bit data word stored in said first, said second, register means, respectively, and receiving said signed-number signal for generating a high-order unsigned/signed generate (GEN ) signal and a high-order unsigned/signed propagate (PROP) signal therefrom; a first and a second lookahead carry logic means receiving said low-order generate and propagate signals and said high-order unsigned/signed generate and propagate signals, for generating therefrom at said first, respectively, said second, output of said bounds checker means, said signal indicative of said first, respectively, said second, selectable relationship; and gate means connected to said first and said second lookahead carry logic means receiving said signals indicative of said first and said second selectable relationships, for generating therefrom at said third output of said bounds checker means said signal indicative of said third selectable relationship; whereby said lower-, respectively upper-limit, plural-bit data word can be conducted via said input data bus to said first register means, respectively, said second register means, and stored therein upon application of a HIGH said first, respectively, said second, load register signal;and whereby said signals formed on said first, second and third outputs of said bounds checker means corresponding to said selectable numeric relationship is generated for either said unsigned, or said signed, respectively, numeric data words depending on whether said signed-number signal is a LOW, or a HIGH, respectively, in a manner which imposes no added time delay compared to the time required by said bounds checker means capable of operating only on either said unsigned or said two's complement notation data words, exclusively.

Claim 10

Bounds checker means according to claim 7 wherein said first, said second, lookahead carry logic means is further responsive to a first, respectively, a second, carry-in signal and wherein said first plurality of low-order logic cell means perform the following logical operations on the signals representing the bit position of said data-word-to-be-compared (D i ) and the complement of the bit position of said data word stored in said first register means, (L i ): wherein said second plurality of low-order logic cell means perform the following logical operations on the signals representing the complement of the bit position of said data-word-to-be-compared (D i ) and the bit position of said data word stored in said second register means (U j ) : wherein said first high-order logic cell means performs the following logical operations on the signals representing the high-order true and complemented bit position of said data-word-to-be-compared (D n , D n ) and the high-order true and complemented bit position of said data word stored in said first register means (L n , L n ): if signed-number signal is a HIGH if signed-number signal is a LOW if signed-number signal is a HIGH if signed-number signal is a LOW, wherein said second high-order logic cell means performs the following logical operations on the signals representing the high-order true and complemented bit position of said data-word-to-be-compared (D , D n ) and the high-order true and complemented bit position of said data word stored in said second register means ( U n' Un); if signed-number signal is a HIGH if signed-number signal is a LOW if signed-number signal is a HIGH if signed-number signal is a LOW, whereby, said bounds checker means performs a subtraction of said data word stored in said first register means from said data-word-to-be-compared using said first carry-in signal as the input to the least-significant bit position to said first lookahead carry logic means generating therefrom a HIGH output signal at said first output of said bounds checker means indicative of said first numeric relationship that said data word stored in said register means is less-than, respectively, less-than-or-equal-to, said data-word-to-be-compared, if said first carry-in signal is a LOW, respectively, a HIGH, said generating therefrom a LOW output signal indicative of said first numeric relationship that said data word stored in said first register means is greater-than-or-equal-to, respectively, greater-than, said data-word-to-be-compared, if said first carry-in signal is a LOW, respectively, a HIGH; and whereby, said bounds checker means performs a subtraction of said data-word-to-be-compared from said data word stored in said second register means using said second carry-in signal as the input to the least-significant bit position to said second lookahead carry logic means generating therefrom a HIGH output signal at said second output of said bounds checker means indicative of said second numeric relationship that said data word stored in said second register means is greater-than-or-equal-to, respectively, greater-than, said data-word-to-be-compared, if said second carry-in signal is a HIGH, respectively, a LOW, and generating therefrom a LOW output signal indicative of said second numeric relationship that said data word stored in said second register means is less-than, respectively, less-than-or-equal-to, said data-word-to-be-compared, if said second carry-in signal is a HIGH, respectively, a LOW, and whereby, a HIGH output signal is generated at said third output of said bounds checker indicative of said third numeric relationship that said data-word-to-be-compared is less-than-or-equal-to, respectively, less-than, said data word stored in said first register means if said first carry-in signal is a LOW, respectively, a HIGH, or that said data-word-to-be-compared is greater-than, respectively, greater-than-or-equal-to, said data word stored in said second register means, if said second carry-in signal is a HIGH, respectively, a LOW and generating at said third output, a LOW output signal indicative of said third numeric relationship that said data-word-to-be-compared is greater-than, respectively, greater-than-or-equal-to, said data word stored in said first register means if said first carry-in signal is a LOW, respectively, a HIGH, and that said data word stored in said second register means is greater-than-or-equal-to, respectively, greater-than, said data-word-to-be-compared, if said second carry-in signal is a HIGH, respectively, a LOW.