EP0186832A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Memory device
Assignee: Toshiba Tec Corp
•
Filing: 1985-12-13
•
Granted: —
•
Expires: 2005-12-13
Abstract
Abstract A memory device includes a reset signal generator (5) for generating a reset signal when an output voltage from a main power supply circuit (1) to supply a driving voltage to a memory (2) decreases to a first predetermined voltage, and a switching circuit (3, 9) for allowing a data holding voltage from a backup power supply (10, 11) to be supplied to the memory (2) in place of the driving voltage from the main power supply circuit (1) in response to the reset signal. This memory device further includes a comparator (7, 12, 13) for generating an inhibiting signal when it detects that the data holding voltage from the backup power supply (10, 11) at the end of the reset signal is lower than the voltage necessary to hold the data in the memory (2), and a control circuit (6, 8, DEC) for setting the memory (2) into the operation inhibition state when it detects that the inhibiting signal was generated from the comparator (7, 12, 13) at the end of the reset signal.
Inventors
- 👤 Tsuyoshi Matsushita
- 👤 Yoshiaki Ito
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 07:17
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/24; G11; G11C; G11C5/00; G11C5/14; G11C5/141; G11C7/00; G11C7/22; G11C7/24
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
270 words
A memory device comprising: memory means (2); a main power supply circuit (1) for applying a driving voltage to said memory means (2); reset signal generating means (5) for generating a reset signal when an output voltage from said main power supply circuit (1) decreases to a first predetermined voltage; a backup power supply circuit (10, 11) for applying a data holding voltage to said memory means (2); and switching means (3, 9) for allowing said data holding voltage from said backup power supply circuit (10, 11) to be applied to the memory means (2) in place of said driving voltage from said main power supply circuit (1) in response to the reset signal from said reset signal generating means (5), characterized by further comprising comparing means (7, 12, 13) for comparing the data holding voltage from the backup power supply circuit (10, 11) with a second predetermined voltage which is needed for the memory means (2) to hold data, thereby generating an output signal corresponding to the result of the comparison when the reset signal from the reset signal generating means (5) is ended, and control means (6, 8, DEC) which checks the output signal from said comparing means (7, 12, 13) in response to the end of the reset signal from said reset signal generating means (5) and sets said memory means (2) into the operation inhibition state in the case where said control means detects that the output signal from the comparing means (7, 12, 13) indicates that the data holding voltage from said backup power supply circuit (10, 11) is lower than said second predetermined voltage.
Claim 2
Dependent Claim
270 words
A memory device comprising: memory means (2); a main power supply circuit (1) for applying a driving voltage to said memory means (2); reset signal generating means (5) for generating a reset signal when an output voltage from said main power supply circuit (1) decreases to a first predetermined voltage; a backup power supply circuit (10, 11) for applying a data holding voltage to said memory means (2); and switching means (3, 9) for allowing said data holding voltage from said backup power supply circuit (10, 11) to be applied to the memory means (2) in place of said driving voltage from said main power supply circuit (1) in response to the reset signal from said reset signal generating means (5), characterized by further comprising comparing means (7, 12, 13) for comparing the data holding voltage from the backup power supply circuit (10, 11) with a second predetermined voltage which is needed for the memory means (2) to hold data, thereby generating an output signal corresponding to the result of the comparison when the reset signal from the reset signal generating means (5) is ended, and control means (6, 8, DEC) which checks the output signal from said comparing means (7, 12, 13) in response to the end of the reset signal from said reset signal generating means (5) and sets said memory means (2) into the operation inhibition state in the case where said control means detects that the output signal from the comparing means (7, 12, 13) indicates that the data holding voltage from said backup power supply circuit (10, 11) is lower than said second predetermined voltage.
Claim 3
Dependent Claim
86 words
A memory device according to claim 1, characterized by further comprising power supply interruption detecting means (4) which generates an output signal when said detecting means (4) detects that the output voltage of the main power supply circuit (1) drops lower than a third predetermined voltage between said first and second predetermined voltages, and in that said control means (6, 8 DEC) sets said memory means (2) into the operation inhibition state in response to the output signal of said power supply interruption detecting means (4).
Claim 4
Dependent Claim
81 words
A memory device according to claim 2, characterized in that said comparing means includes a reference voltage generator (13) for generating said second predetermined voltage, a comparator (12) for comparing the output voltage of the backup power supply circuit (10, 11) with the output voltage of said reference voltage generator (13), and a signal holding circuit (7) for holding the output signal of said comparator (12) in response to the end of the reset signal from said reset signal generator (5).
Claim 5
Dependent Claim
81 words
A memory device according to claim 2 or 3, characterized in that said control means comprises a control circuit (6, DEC) for generating a nonoperating signal in response to the output signal of said power supply interruption detecting means (4) and a logic circuit (8) for setting said memory means (2) into the operation inhibition state in response to at least one reset signal from the reset signal generating means (5) and the nonoperating signal from said control circuit (6, DEC).
Claim 6
Dependent Claim
81 words
A memory device according to claim 1, characterized in that said comparing means includes a reference voltage generator (13) for generating said second predetermined voltage, a comparator (12) for comparing the output voltage of the backup power supply circuit (10, 11) with the output voltage of said reference voltage generator (13), and a signal holding circuit (7) for holding the output signal of said comparator (12) in response to the end of the reset signal from said reset signal generator (5).
Claim 7
Dependent Claim
91 words
A memory device according to any one of preceding claims, characterized in that said switching means comprises a delay circuit (9) for delaying the reset signal from said reset signal generating means (5) by only a predetermined time and a switch (3) for allowing the data holding voltage from said backup power supply circuit (10, 11) to be supplied to said memory means (2) in place of the driving voltage of said main power supply circuit (1) in response to the reset signal which is supplied through said delay circuit (9).
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.