EP0186459A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory incorporating a test pattern generator
Assignee: Fujitsu Ltd
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Filing: 1985-12-20
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Granted: —
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Expires: 2005-12-20
Abstract
Abstract In a semiconductor device comprising a memory cell array (1) and a test pattern generating circuit (8), the test pattern generating circuit generates a test pattern and transmits the test pattern to the memory cell array when receiving both a least significant bit signal (A o ) of address signals (A o ... A n ) supplied to the memory cell array, and a control signal (CNT1).
Inventors
- 👤 Mitsugu Naitoh
- 👤 Yoshiyuki Suehiro
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 23:36
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/46; G11C29/14; G11C29/56; G11C29/56004
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
65 words
A semiconductor device comprising: a memory cell array; a test pattern generating circuit; and means for receiving a control signal from the outside; said test pattern generating circuit being operable for generating a test pattern and transmitting said test pattern to said memory cell array when receiving a least significant bit signal of address signals supplied to said memory cell array and said control signal.
Claim 2
Dependent Claim
65 words
A semiconductor device comprising: a memory cell array; a test pattern generating circuit; and means for receiving a control signal from the outside; said test pattern generating circuit being operable for generating a test pattern and transmitting said test pattern to said memory cell array when receiving a least significant bit signal of address signals supplied to said memory cell array and said control signal.
Claim 3
Dependent Claim
34 words
A semiconductor device according to claim 1, wherein said test pattern is able to be generated in said test pattern generating circuit by logically processing said least significant bit signal and said control signal.
Claim 4
Dependent Claim
50 words
A semiconductor device according to claim 1, wherein said test pattern is able to be generated in said test pattern generating circuit by logically processing said least significant bit signal, an inverted signal of said least significant bit signal, said control signal, and an inverted signal of said control signal.
Claim 5
Dependent Claim
66 words
A semiconductor device according to claim 1, wherein said address signals comprise row address signals and column address signals, and said test pattern is able to be generated in said test pattern generating circuit by logically processing the least significant bit signal of row address signals, the least significant bit signal of column address signals, said control signal, and an inverted signal of said control signal.
Claim 6
Dependent Claim
25 words
A semiconductor device according to any preceding claim, wherein the test pattern consists of test data of alternate "0"'s and "1"'s constituting a checkerboard pattern.
References Cited (Backward Citations)
No citation records indexed.
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