Digital switching system with two-directional addressing rams

Claim 2

A digital switching system for providing time division multiplex digital communication of parallel sequential signals of N words each of M bit length between N telephone/data subscribers over N transmission lines comprising: a) a first array of memory devices having N columns and M rows of memory for storing the N words each M bits long from the N subscribers; b) parallel-to-serial means coupled by M lines to said first array for providing a time division multiplexed serial digital bit stream of N words each M bits in length from the contents of said memory; c) a transmission line coupled to said parallel-to-serial means; d) a serial-to-parallel means for accumulating the serial digital bit stream from the transmission line and providing an output of N words on M parallel lines; e) a second array of memory devices coupled to said M lines of said serial-to-parallel means for receiving said N words, said second array having N columns and M rows of memory for storing the N words in M rows of N words each M bits long; f) coupling means for coupling the N words each M bits long to the N telephone/data subscribers over said transmission lines.

Claim 3

The system of Claim 1 wherein each memory device comprises storage means addressable in two directions.

Claim 4

The system of Claim 1 wherein each memory device includes a storage element coupled to a pair of first and second transistor switches, said switches being separately enabled such that bits stored in each storage element may be written into storage on a first line by enabling the first transistor and written out on a second line by enabling the second transistor.

Claim 5

The system of Claim 1 wherein N > M.

Claim 6

A private automatic branch exchange for providing time division multiplex digital communication and switching of parallel sequential signals of N words each of M bit length plus an additional signalling bit associated with each N word between N telephone/data subscribers over N transmission lines comprising: a) an input array of memory devices having N columns and M rows of memory for reading into memory, the N words each M bits long from the N lines into the N columns and M rows of memory; b) an output array of memory devices having N columns and M rows of memory; c) a signalling array of memory devices having N columns and M rows of memory into which each signalling bit is written in sequence; d) a source array of memory devices; e) computer means for determining from the signal bits the subscriber source address from which the signal bit came and storing such source address information in said source array and for reading the contents of said input array into said output array in a sequence determined by the source address information in said source array.

Claim 7

A private automatic branch exchange for providing time division multiplex digital communication and switching of parallel sequential signals of N words each of M bit length plus an additional signalling bit associated with each N word between N telephone/data subscribers over N transmission lines comprising: a) an input array of memory devices having N columns and M rows of memory for reading into memory, the N words each M bits long from the N lines into the N columns and M rows of memory; b) an output array of memory devices having N columns and M rows of memory; c) a signalling array of memory devices having N columns and M rows of memory into which each signalling bit is written in sequence; d) a source array of memory devices; e) computer means for determining from the signal bits the subscriber source address from which the signal bit came and storing such source address information in said source array and for reading the contents of said input array into said output array in a sequence determined by the source address information in said source array.

Claim 8

The exchange of Claim 5 in which the output array is read out in M words N bits long for transmission over the N transmission lines to the N telephone data subscribers.

Claim 9

The exchange of Claim 5 in which each memory device comprises storage means addressable in two directions.

Claim 10

The exchange of Claim 7 in which each storage means is coupled to a pair of first and second transistor switches each of which may be separately enabled to permit writing into a first set of lines of the array by enabling the first transistor switches and written out on a second set of lines of the array by enabling the second transistor switches.

Claim 11

A digital switching system for providing time division multiplex digital communication of parallel sequential signals of N words each of M bit length between N telephone/data subscribers over N pairs of conductors each forming a transmission line having a characteristic impedance of Z o and wherein a transmitter and receiver is located at each subscriber and is coupled to said pairs of conductors comprising: a) a first array of memory devices having N columns and M rows of memory for storing the N words each M bits long from the N subscribers; b) parallel-to-serial means coupled by M lines to said first array for providing a time division multiplexed serial digital bit stream of N words each M bits in length from the contents of said memory; c) said transmitters being coupled at an input side to said parallel-to-serial means and at an output side to said pairs of conductor; d) said receivers being coupled at an input side to said pairs of conductors and at an output side to a serial-to-parallel means for accumulating the serial digital bit stream from the transmission line and providing an output of N words on M parallel lines; e) a second array of memory devices coupled to said M lines of said serial-to-parallel means for receiving said N words, said second array having N columns and M rows of memory for storing the N words in M rows of N words each M bits long; f) coupling means for coupling the N words each M bits long to the N telephone/data subscribers over said transmission lines; g) the source impedance of said transmitters being matched to said characteristic impedance and the input impedance of said receivers being high enough to present an effective short to received signals.

Claim 12

A digital switching system for providing time division multiplex digital communication of parallel sequential signals of N words each of M bit length between N telephone/data subscribers over N pairs of conductors each forming a transmission line having a characteristic impedance of Z o and wherein a transmitter and receiver is located at each subscriber and is coupled to said pairs of conductors comprising: a) a first array of memory devices having N columns and M rows of memory for storing the N words each M bits long from the N subscribers; b) parallel-to-serial means coupled by M lines to said first array for providing a time division multiplexed serial digital bit stream of N words each M bits in length from the contents of said memory; c) said transmitters being coupled at an input side to said parallel-to-serial means and at an output side to said pairs of conductor; d) said receivers being coupled at an input side to said pairs of conductors and at an output side to a serial-to-parallel means for accumulating the serial digital bit stream from the transmission line and providing an output of N words on M parallel lines; e) a second array of memory devices coupled to said M lines of said serial-to-parallel means for receiving said N words, said second array having N columns and M rows of memory for storing the N words in M rows of N words each M bits long; f) coupling means for coupling the N words each M bits long to the N telephone/data subscribers over said transmission lines; g) the source impedance of said transmitters being matched to said characteristic impedance and the input impedance of said receivers being high enough to present an effective short to received signals.

Claim 13

The apparatus of Claim 9 in which the signals comprise voltage pulses which undergo logical transitions and wherein power is only dissipated during such transitions.

Claim 14

The apparatus of Claim 9 in which the transmitters comprise differential drivers coupled across said conductors.

Claim 15

A private automatic branch exchange communication system for providing time division multiplex digital communication and switching of parallel sequential signals comprising voltage pulses of N words each of M bit length plus an additional signalling bit associated with each N word between N telephone/data subscribers over N transmission lines of first and second wires each simultaneously in opposite directions comprising: a) an input array of memory devices having N columns and M rows of memory for reading into memory, the N words each M bits long from the N lines into the N columns and M rows of memory; b) an output array of memory devices having N columns and M rows of memory; c) a signalling array of memory devices having N columns and M rows of memory into which each signalling bit is written in sequence; d) a source array of memory devices; e) computer means for determining from the signal bits the subscriber destination address and storing such source address information in said source array and for reading the contents of said input array into said output array in a sequence determined by the source address information in said source array; f) read output means for reading out the output array in M words N bits long for transmission by a first transmitter over the N transmission lines to the N telephone data subscribers each of which has a second transmitter for transmitting. N words M bits long to said exchange and wherein: i) the first transmitter at the exchange generates a first voltage onto the first of said wires; ii) the transmitter at the subscriber's generates a second voltage onto the first of said wires; iii) the second of said wires is grounded at each end; iv) impedance matching resistors, matched to the impedance of said two wires, are coupled between each of said transmitters and said first wire; and v) a first subtractor circuit is provided at the exchange for linearly subtracting a signal proportional to the first voltage from the signal propagated on the first wire in the direction from the subscribers to the exchange to produce at the output of the subtractor circuit a difference signal which is proportional to the delayed and attenuated version of the second voltage; and vi) a second subtractor circuit at the subscribers for linearly subtracting a signal proportional to the second voltage from the signal propagating on the first wire in the direction from the exchange to the subscribers to produce at the output of the second subtractor circuit a difference signal which is proportional to the delayed and attenuated version of the first voltage.

Claim 16

A private automatic branch exchange communication system for providing time division multiplex digital communication and switching of parallel sequential signals comprising voltage pulses of N words each of M bit length plus an additional signalling bit associated with each N word between N telephone/data subscribers over N transmission lines of first and second wires each simultaneously in opposite directions comprising: a) an input array of memory devices having N columns and M rows of memory for reading into memory, the N words each M bits long from the N lines into the N columns and M rows of memory; b) an output array of memory devices having N columns and M rows of memory; c) a signalling array of memory devices having N columns and M rows of memory into which each signalling bit is written in sequence; d) a source array of memory devices; e) computer means for determining from the signal bits the subscriber destination address and storing such source address information in said source array and for reading the contents of said input array into said output array in a sequence determined by the source address information in said source array; f) read output means for reading out the output array in M words N bits long for transmission by a first transmitter over the N transmission lines to the N telephone data subscribers each of which has a second transmitter for transmitting. N words M bits long to said exchange and wherein: i) the first transmitter at the exchange generates a first voltage onto the first of said wires; ii) the transmitter at the subscriber's generates a second voltage onto the first of said wires; iii) the second of said wires is grounded at each end; iv) impedance matching resistors, matched to the impedance of said two wires, are coupled between each of said transmitters and said first wire; and v) a first subtractor circuit is provided at the exchange for linearly subtracting a signal proportional to the first voltage from the signal propagated on the first wire in the direction from the subscribers to the exchange to produce at the output of the subtractor circuit a difference signal which is proportional to the delayed and attenuated version of the second voltage; and vi) a second subtractor circuit at the subscribers for linearly subtracting a signal proportional to the second voltage from the signal propagating on the first wire in the direction from the exchange to the subscribers to produce at the output of the second subtractor circuit a difference signal which is proportional to the delayed and attenuated version of the first voltage.