Multiprocessor system

Claim 2

A multiprocessor system having a bus (13) for transmitting data, and a plurality of multiprocessor modules (11) for performing a predetermined data processing task and connected to said bus (13), characterized in that each of said processor modules (11) comprises: means (21, 61, 71) for disconnecting said processor module (11) from said bus (13) when a stop request is issued toward said processor module (11) during the access by said processor module (11); memory means (55, 57, 63, 65) for storing the contents of the access by said processor module (11) to said bus (13) when the stop request is issued to said processor module (11); and control means (31, 51, 53, 61, 67, 69, 71, 73) for executing the same bus access which said processor module (11) was performing when the stop request was issued, in accordance with the contents of said memory means (55, 57, 63, 65) after the stop request has been cancelled, and for causing said processor module (11) to process data, when the bus access reaches the same condition as said processor module (11) was executing on the bus (13) when the stop request was issued.

Claim 3

A multiprocessor system according to claim 1, characterized in that each of said processor modules (11) includes stop request means (47) to request the stop of said multiprocessor module (11).

Claim 4

A multiprocessor system according to claim 1, characterized in that said multiprocessor module (11) includes: clock signal generating means (29) for generating a clock signal; operation processing means (45) connected to said clock signal generating means (29) and for executing a predetermined data processing according to a predetermined program in response to said clock signal; and stop request means (47) connected to said clock signal generating means (29) and for stopping the generation of the clock signal by said clock signal generating means (29), and said control means (31, 51, 53, 61, 67, 69, 71, 73) connected to said clock signal generating means (29), said bus (13), and said operation processing means (45), and for prohibiting the supply of the clock signal to said operation processing means (45) after the stop of the clock signal generation is removed by said stop request means (47), and for restarting, on the basis of the contents of said memory means (55, 57, 63, 65), the bus access which was made to said bus (13) by said operation processing means (45), and for supplying the clock signal to said operation processing means (45) after a state of the bus access coincides with that as the clock signal generation was stopped.

Claim 5

A multiprocessor system according to claim 3, characterized in that said memory means (55, 57, 63, 65) stores the type and state of the bus access which was made by said operation processing means (45) to said bus (13); and said control means (31, 51, 53, 61, 67, 69, 71, 73), after the supply of the clock signal is restarted, restarts said bus access on the basis of said access type stored in said memory means (55, 57, 63, 65), and supplies the clock signal to said operation processing means (45) when a state of the bus access by said control means coincides with that stored in said memory means (65).

Claim 6

A multiprocessor system according to claim 4, characterized in that said memory means includes: bus access type memory means (63) for storing said bus access type; and access state memory means (65) for storing to what clock of one bus cycle of the clock signal generated by said clock signal generating means (29) the bus access proceeds; and said control means (31, 51, 53, 61, 67, 69, 71, 73), when the clock signal is being supplied, transfers information between said operation processing means (45) and said bus (13), when the clock is stopped, electrically disconnects said operation processing means (45) from said bus (13), when the supply of said clock signal is restarted, arbitrates the use of said bus (13) between said processor module containing said control means and other processor modules (11) and restarts bus access based on said bus access type of said bus access type memory means (63) to said bus (13), and when the number of clocks of the clock signal after its supply is restarted is coincident with that of the clocks stored in said access state memory means (65), supply again to said operation processing means (45) the clock signal and transfer the information between said operation processing means (45) and said bus (13).

Claim 7

A multiprocessor system according to claim 5, characterized in that said bus access state memory means (63) includes a counter which is cleared every bus cycle in response to the clock signal, and said control means (31, 51, 53, 61, 67, 69, 71, 73) includes access detecting means (69) containing a counter for counting the number of clocks after the supply of the clock signal is restarted, and comparing means (73) for comparing the data output from said access detecting means (69) and the data output from said access state memory means (65), said control means (31, 51, 53, 61, 67, 69, 71, 73) supplying said clock signal to said operation processing means (45) after both said data are coincident with each other in said comparing means (73).

Claim 8

A multiprocessor system according to claim 1, - characterized in that said multiprocessor module (11) includes: bus arbitration means (21) connected to said bus (13) and for arbitrating the use of said bus (13) between said processor module (11) Containing this bus arbitration means and other multiprocessor modules (11); bus access control means (23) connected to said bus (13) and for controlling the bus access; address output means (25) connected to said bus (13) and for producing an address necessary for the bus access; data input/output means (27) connected to said bus (13) and for inputting and outputting data; clock signal generating means (29) for generating a clock signal; stop request means (47) connected to said clock signal generating means (29) and for requesting the stop of the clock signal supply; and operation processing means (45) for executing the data processing according to a predetermined program, in response to said clock signal, said control means operating such that, when the stop of the clock signal supply is requested, said control means controls said bus arbitration means (21) to electrically disconnect said multiprocessor module (11) from said bus (13), after the request of the clock signal supply stop is removed, said control means controls, on the basis of the contents 6f said memory means (55, 57, 63, 65), said bus arbitration means (21), said bus access control means (23), said address output means (25) and said data input/output means (27), to execute the bus access as was stopped, from its beginning, and when a state of the bus access coincides with that at the stoppage of the bus access, said control means restarts the supply of the clock signal to said operation processing means (45) to operate said operation processing means (45).

Claim 9

A multiprocessor system according to claim 7, characterized in that said memory means includes: bus access type memory means (63) for storing a bus access type of the bus access which was made by said operation processing means (45) to said external bus at the stoppage of the clock signal supply, and access state memory means (65) for storing to what clock of one bus cycle said bus access proceeds; and characterized in that said control means (31, 51, 53, 61, 67, 69, 71, 73) includes: means (61, 67) for prohibiting the supply of a buss access request output from said operation processing means (45) when said stop request means (47) requests the stop of the clock signal, and for electrically disconnecting said processor module (11) from said bus (13); restart means (51, 53, 61, 67, 71) operating such that, when said stop request means (47) removes the request of stopping the supply of the clock signal, said restart means supplies the bus access type stored in said bus access type memory means (63) to said bus arbitration means (21), and gains the right of using said bus (13), and said restart means controls said bus access control means (23), said address output means (25) and said data input/output means (27) to restart the bus access which was made by said operation processing means (45) at the time of stoppage of the clock signal; access detecting means (69) for counting the number of clocks of the clock signal after the supply of said clock signal is restarted; and means (51, 53, 61, 69, 71, 73) for comparing the number of clocks detected by said access detecting means (69) with that stored in said access state memory means (65), and for restarting the supply of the clock signal to said operation processing means (45) when both the numbers of clocks are equal to each other, and for causing said operation processing means (45) to execute again the bus access after the stop of the clock signal supply.

Claim 10

A multiprocessor system according to claim 7, characterized in that said access state memory means (65) includes a counter which is cleared every bus cycle in response to the clock signal, and said access detecting means (69) includes a counter for counting the number of clocks after the supply of the clock signal is restarted.

Claim 11

A processor module comprising: bus arbitration means connectable to an external bus and for arbitrating the use of said external bus between said processor module and other ones, in response to a bus access command; address output means connectable to said external bus and for outputting an address to said external bus; data input/output means connectable to said external bus and for transferring data to and from said external bus; . bus access control means connectable to said external bus and for controlling said address output means and said data input/output means in response to said bus access command; clock signal generating means for generating a clock signal; operation processing means (45) for processing data according to a predetermined program in response to the clock signal; and stop control means connected to said bus arbitration means, said bus access control means, said address output means, said data input/output means, said clock signal generating means, said stop request means, and said operation processing means (45), said stop control means operating such that, when said stop request means requests the stop of supplying the clock signal, said stop control means stores the contents of a bus access as was made by said stop request means and controls said bus arbitration means to stop the bus access by said processor module, and when the request of stopping the supply of the clock signal is removed and the supply of the clock signal is restarted, said stop control means restarts the bus access as was stopped, on the basis of the contents and a state of the bus access, and when a state of the bus access coincides with that when the clock signal supply stop is requested, said stop control means restarts the supply of the clock signal to said operation processing means.

Claim 12

A processor module comprising: bus arbitration means connectable to an external bus and for arbitrating the use of said external bus between said processor module and other ones, in response to a bus access command; address output means connectable to said external bus and for outputting an address to said external bus; data input/output means connectable to said external bus and for transferring data to and from said external bus; . bus access control means connectable to said external bus and for controlling said address output means and said data input/output means in response to said bus access command; clock signal generating means for generating a clock signal; operation processing means (45) for processing data according to a predetermined program in response to the clock signal; and stop control means connected to said bus arbitration means, said bus access control means, said address output means, said data input/output means, said clock signal generating means, said stop request means, and said operation processing means (45), said stop control means operating such that, when said stop request means requests the stop of supplying the clock signal, said stop control means stores the contents of a bus access as was made by said stop request means and controls said bus arbitration means to stop the bus access by said processor module, and when the request of stopping the supply of the clock signal is removed and the supply of the clock signal is restarted, said stop control means restarts the bus access as was stopped, on the basis of the contents and a state of the bus access, and when a state of the bus access coincides with that when the clock signal supply stop is requested, said stop control means restarts the supply of the clock signal to said operation processing means.

Claim 13

A processor module according to claim 10, characterized in that said stop control means includes: means for storing a bus access command of the bus access as made said operation processing means at the time of that stoppage; means for storing to what clock of one bus cycle said bus access proceeds; means for prohibiting a bus access command output from said operation processing means from being supplied to said bus arbitration means when said stop request means requests the stop of supplying the clock signal, and for disconnecting said processor module from said bus; restarting means operating such that, when said stop request means removes the request of stopping the supply of the clock signal, said restarting means supplies a bus access command stored in said bus access command memory means to said bus arbitration means, and gains the right to use of said bus, controls said bus access control means, said address output means, and said data input/output means, and finally restarts the bus access as was made by said operation processing means at the time of stopping the clock signal supply; and means for restarting the supply of the clock signal to said operation processing means when the number of clocks of the clock signal after the restart of supplying the clock signal is equal to that stored in said access state memory means, and allows said operation processing means to make the access after the stoppage of the clock signal supply.

Claim 14

A multiprocessor system according to claim 11, characterized in that said access state memory means (65) includes a counter which is cleared for each bus cycle in response to said clock signal; and said access detecting means (69) includes a counter for counting the number of clocks after the restart of supplying the clock signal.