EP0185779A1
Expired / Lapsed
EP
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Digital phase locked loop
Assignee: International Business Machines Corp
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Filing: 1984-12-21
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Granted: —
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Expires: 2004-12-21
Abstract
Abstract A phase locked loop (PLL) arrangement comprising a local crystal oscillator (23) and a tapped delay chain (15) of analog delay elements (17). Connected to the delay chain taps are a flash register (25) consisting of latches which store the tap signal values at each data signal transition, and an output multiplexer (37) for selecting one of the tap signals as phase shifted output clock. Contents of the flash register are encoded by an encoder (33) which furnishes a value representing the phase offset between data signal and local clock signal. By a look-up table (41), the phase offset is converted to a phase selection value controlling the output multiplexer. The delay chain serves two purposes: Phase offset detection and clock signal phase shifting. No sampling or control signals are used which have a higher frequency than that of the system clock.
Inventors
- 👤 Erwin Alex Zurfluh
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 06:12
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/081; H03L7/0812; H03L7/0814; H04; H04L; H04L7/00; H04L7/02; H04L7/033; H04L7/0337; H04L7/0338
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
137 words
Digital phase locked loop (PLL) arrangement comprising - a fixed frequency oscillator (23) providing a basic bi-level clock signal, - a tapped delay chain (15) connected to said oscillator for receiving said basic bi-level clock signal, - evaluation means (25, 33, 41/43) connected to the taps (19, 21-1 ... 21-n) of said delay chain and responsive to each transition of a control signal furnished to a control input (27) of it for generating a phase selection signal (39) from a set of momentary tap signal values, and - output gating means (37) connected to said delay chain taps (19, 21-1 ... 21-n) and to said evaluation means (25, 33, 41/43) and being responsive to said phase selection signal (39) for selectively gating the signal from one of said delay chain taps to a clock output line (13).
Claim 2
Dependent Claim
137 words
Digital phase locked loop (PLL) arrangement comprising - a fixed frequency oscillator (23) providing a basic bi-level clock signal, - a tapped delay chain (15) connected to said oscillator for receiving said basic bi-level clock signal, - evaluation means (25, 33, 41/43) connected to the taps (19, 21-1 ... 21-n) of said delay chain and responsive to each transition of a control signal furnished to a control input (27) of it for generating a phase selection signal (39) from a set of momentary tap signal values, and - output gating means (37) connected to said delay chain taps (19, 21-1 ... 21-n) and to said evaluation means (25, 33, 41/43) and being responsive to said phase selection signal (39) for selectively gating the signal from one of said delay chain taps to a clock output line (13).
Claim 3
Dependent Claim
42 words
Arrangement according to claim 1, characterized in that - said delay chain (15) comprises n delay elements (17-1, 17-2, ... 17-n) each having a delay of T/(n+l), with T being the period of said bi-level clock signal furnished by said oscillator (23).
Claim 4
Dependent Claim
102 words
Arrangement according to claim 1, characterized by - delay length encoding means (47) being connected to the input tap (19) and to the last k taps (21-(n-k-1), 21-(n-k-2), ... 21n) of said delay chain (15), and having output lines (49) connected to said evaluation means (25, 33, 43), for providing an identification of the last one of said k taps whose present signal value corresponds to the present signal value on said input line (19), - whereby an indication of an effective delay line length with respect to the clock signal period of said oscillator (23) is furnished to said evaluation means.
Claim 5
Dependent Claim
71 words
Arrangement according to claim 1, characterized in that - said evaluation means (25, 33, 41/43) comprises storage means (25)' being connected to the delay chain taps (19, 21-1 ... 21-n) and having a load control input line (27), for storing, in response to occurrence of a control signal transition at its control input line (27), a sequence of binary values representing the clock signal values present at all delay chain taps.
Claim 6
Dependent Claim
75 words
Arrangement according to claim 4, characterized in that - said storage means (25) is an array of binary edge-triggered latches, each having a load control input that is connected to the common load control input line (27), and that - the two signal levels of the bi-level clock signal generated by said local oscillator (23) and the two logic input signal levels of said binary latches of said storages means (25) correspond to each other.
Claim 7
Dependent Claim
54 words
Arrangement according to claim 4, characterized in that - said evaluation means (25, 33, 41/43) further comprises encoder means (33) connected to. outputs of said storage means (25) for generating, on an output line (35) a phase offset signal value OFF in response to the sequence of binary values stored in said storage means.
Claim 8
Dependent Claim
67 words
Arrangement according to claim 6, characterized in that - said evaluation means (25, 33, 41) further comprises table look-up means (41) connected to the output (35) of said encoder means (33) and having a plurality of phase selection signals stored therein, which furnishes at its output one of said phase selection signals in response to a phase offset signal φ OFF received from the encoder output (35).
Claim 9
Dependent Claim
78 words
Arrangement according to claim 6, characterized in that - said evaluation means (25, 33, 43) further comprises a processor (43) connected to the output (35) of said encoder means (33) for receiving said phase offset signal φ OFF ' and for generating in response to current phase offset value and previous phase offset values, a phase selection signal that is furnished at an output (39) which is connected to a control input of said output gating means (37).
Claim 10
Dependent Claim
49 words
Arrangement according to claim 4, characterized in that - a Schmitt trigger (29) is provided whose output is connected to the load control input line (27) of said storage means (25), and whose input is connected to a PLL input line (11) to which the data signal is applied.
Claim 11
Dependent Claim
124 words
Method for providing a clock signal synchronized to a received data signal, characterized by the steps of: - locally generating a bi-level clock signal of given frequency; - feeding said bi-level clock signal to a tapped delay chain; - obtaining the set of momentary signal values available at all taps of said delay chain when a level transition in the received data signal occurs; and - determining a selection value in response to said set of momentary signal values, for selecting one of said taps of said delay chain; whereby said delay chain is used simultaneously for determining a phase offset by evaluating its tap output values and for obtaining a phase shifted clock signal by selecting one of its taps as clock output.
Claim 12
Dependent Claim
124 words
Method for providing a clock signal synchronized to a received data signal, characterized by the steps of: - locally generating a bi-level clock signal of given frequency; - feeding said bi-level clock signal to a tapped delay chain; - obtaining the set of momentary signal values available at all taps of said delay chain when a level transition in the received data signal occurs; and - determining a selection value in response to said set of momentary signal values, for selecting one of said taps of said delay chain; whereby said delay chain is used simultaneously for determining a phase offset by evaluating its tap output values and for obtaining a phase shifted clock signal by selecting one of its taps as clock output.
Claim 13
Dependent Claim
43 words
Method according to claim 10, characterized in that - a control signal edge is derived from each data input signal transition, and that each control signal edge controls the transfer of all tap output values of the delay chain to a storage array.
Claim 14
Dependent Claim
37 words
Method according to claim 11, characterized in that - a phase offset value is generated by encoding the ensemble of all said tap output values available in said storage array, in accordance with a given coding rule.
Claim 15
Dependent Claim
57 words
Method according to claim 12, characterized in that - said phase offset value is used as an address tor accessing a stored phase selection value contained in a stored look-up table of phase selection values, and that - said accessed phase selection value is used for controlling the selection of one of said delay chain tap outputs.
References Cited (Backward Citations)
GB2069263A
Cited
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