EP0185504A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A binary subtraction circuit
Assignee: RCA Licensing Corp
•
Filing: 1985-12-10
•
Granted: —
•
Expires: 2005-12-10
Abstract
Abstract A binary subtracter stage for subtracting single bit binary numbers includes a first exclusive OR gate (18) to which the numbers to be subtracted are applied. The output of the exclusive OR gate is connected to one input of a second exclusive OR gate (20) which has a second input connected to a borrow input signal (10). The output of the second exclusive OR gate provides the difference between the single bit binary numbers. A borrow output signal (32) is generated with the combination of a pass transistor (22) coupled between the borrow input and borrow output terminals and a three state logic circuit (24, 26. 28, 30) which has its output terminal connected to the borrow output terminal. The pass transistor is controlled by the output of the first exclusive OR gate and the three state logic circuit is controlled by the single bit binary numbers to be subtracted.
Inventors
- 👤 John Armer
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 13:08
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/503
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
200 words
A binary subtracter stage for subtracting a first single bit binary number Y from a second single bit binary number X comprising: first and second binary input terminals (14,12 ) for applying binary numbers X and Y respectively; a borrow output terminal; a borrow input terminal for applying a borrow input signal Bin; characterized by exclusive OR circuitry (18,20) having input terminals coupled to said first and second binary input terminals and said borrow input terminal for producing the difference values of X-Y at an output terminal thereof responsive to the logic function (XOYOBin); coupling means (22) coupled to said first and second binary input terminals for selectively coupling the borrow output terminal to the borrow input terminal when the numbers X and Y are equal; and a three state logic circuit (24-30) having first and second input terminals coupled to said first and second binary input terminals, and having an output terminal coupled to said borrow output terminal, said three state logic circuit generating a first logic output state for the value of Y greater than X, generating a second logic output state for the value of X greater than Y and generating a high impedance output state otherwise.
Claim 2
Dependent Claim
200 words
A binary subtracter stage for subtracting a first single bit binary number Y from a second single bit binary number X comprising: first and second binary input terminals (14,12 ) for applying binary numbers X and Y respectively; a borrow output terminal; a borrow input terminal for applying a borrow input signal Bin; characterized by exclusive OR circuitry (18,20) having input terminals coupled to said first and second binary input terminals and said borrow input terminal for producing the difference values of X-Y at an output terminal thereof responsive to the logic function (XOYOBin); coupling means (22) coupled to said first and second binary input terminals for selectively coupling the borrow output terminal to the borrow input terminal when the numbers X and Y are equal; and a three state logic circuit (24-30) having first and second input terminals coupled to said first and second binary input terminals, and having an output terminal coupled to said borrow output terminal, said three state logic circuit generating a first logic output state for the value of Y greater than X, generating a second logic output state for the value of X greater than Y and generating a high impedance output state otherwise.
Claim 3
Dependent Claim
151 words
The subtracter stage set forth in claim 1 characterized in that the three state logic circuit comprises: first (26) and second (24) transistors of a first type having primary conduction paths serially coupled between said borrow output terminal and a point of potential corresponding to said first logic level, and having respective control electrodes; third (30) and fourth (28) transistors of a second type complementary to said first type, having primary conduction paths serially coupled between said borrow output terminal and a point of potential corresponding to said second logic level, and having respective control electrodes; the control electrodes of said first (26) and fourth (28) transistors being coupled to said first binary input terminal (14); an inverter circuit (16) having an input terminal connected to said second binary input terminal ( 12 ) and an output terminal connected to the control electrodes of said second (24) and third (30) transistors.
Claim 4
Dependent Claim
122 words
The subtraction circuit set forth in claim 1 characterized in that the three state logic circuit comprises: first (50) and second (51) transistors of first and second complementary types respectively, having principal conduction paths serially coupled between said borrow output terminal and a point of potential corresponding to said first logic level, and having respective control electrodes connected to said first (14) and second (12) binary input terminals respectively; third (52) and fourth (53) transistors of said first and second complementary types respectively, having principal conduction paths serially coupled between said borrow output terminal and a point of potential corresponding to said second logic level, and having respective control electrodes coupled to the second (12) and first (14) binary input terminals respectively.
Claim 5
Dependent Claim
193 words
The binary subtracter stage according to claim 1, 2 or 3, characterized in that: said exclusive OR circuitry comprises a first XOR gate (18) having first (14) and second (12) input terminals coupled to said first and second binary input terminals respectively, and having an output terminal, and a second XOR gate (20) having first and second input terminals coupled respectively to said borrow input terminal and the output terminal of said first XOR gate, and having an output terminal (34) for producing the difference of X minus Y; said coupling means comprises: a pass transistor (22) having a primary conduction path coupled between said borrow input (10) and borrow output (32) terminals, and having a control electrode coupled to the output terminal of said first XOR gate (18); and the said three state logic circuit generates a logic one for said first logic output level according to the logic function XY, a logic zero for said second logic output level according to the logic function X9 and said high impedance output state otherwise, where the terms X and Y connote the logic complement of the binary values of X and Y respectively.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.