EP0184828A2
Expired / Lapsed
EP
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Vector processing apparatus
Assignee: Hitachi Ltd
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Filing: 1985-12-11
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Granted: —
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Expires: 2005-12-11
Abstract
Abstract @ The vector processing apparatus fetches vector operands designated by an instruction from a storage (104, 105) to an operand buffer (707, 708) in a vector processor (7). The vector processor reads out and processes the elements of the vector operands stored in the operand buffer. The vector processor controls fetching of the element to be next processed from the operand buffer in accordance with the operation result. Thus, a vector operation of a type in which the increment of the indices of the vector operands depends on the operation result is carried out.
Inventors
- 👤 Yaoko Nakagawa
- 👤 Koichi Ishii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 05:23
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30007; G06F9/30021; G06F15/00; G06F15/76; G06F15/80; G06F15/8053; G06F15/8076; G06F9/30032; G06F9/30036
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
149 words
A vector processing apparatus comprising: memory means (104, 105) for storing a plurality of vector operands; instruction means (3) for instructing a start addresses and maximum numbers of elements of vector operands by an instruction; address control means (2) for controlling fetching of the elements of the vector operands from said memory means in accordance with the start addresses supplied from said instruction means; vector processing means (7) for processing the elements of the vector operands fetched from said memory means and determining the element to be next processed in accordance with an operation result of the elements; said vector processing means including buffer means (707, 708) for storing the elements of the vector operands fetched from said memory means and control means (713, 706, 709, 710 and 711) for controlling fetching of the element to be next processed from said buffer means in accordance with said operation result.
Claim 2
Dependent Claim
149 words
A vector processing apparatus comprising: memory means (104, 105) for storing a plurality of vector operands; instruction means (3) for instructing a start addresses and maximum numbers of elements of vector operands by an instruction; address control means (2) for controlling fetching of the elements of the vector operands from said memory means in accordance with the start addresses supplied from said instruction means; vector processing means (7) for processing the elements of the vector operands fetched from said memory means and determining the element to be next processed in accordance with an operation result of the elements; said vector processing means including buffer means (707, 708) for storing the elements of the vector operands fetched from said memory means and control means (713, 706, 709, 710 and 711) for controlling fetching of the element to be next processed from said buffer means in accordance with said operation result.
Claim 3
Dependent Claim
33 words
A vector processing apparatus according to Claim 1 wherein said vector processing means includes element count means for counting the number of elements of the vector operands processed by said vector processing means.
Claim 4
Dependent Claim
25 words
A vector processing apparatus according to Claim 2 wherein said element count means is updated by said control means in accordance with said operation result.
Claim 5
Dependent Claim
45 words
A vector processing apparatus according to Claim 3 wherein said control means includes means (700, 701, 702, 731, 732, 733) for determining the end of operation based on the maximum numbers of elements of the vector operands and the count of said element count means.
Claim 6
Dependent Claim
22 words
A vector processing apparatus according to Claim 4 wherein said control means includes compare means for comparing elements of two vector operands.
Claim 7
Dependent Claim
47 words
A vector processing apparatus according to Claim 4 wherein said vector processing means includes means (714, 715) for one of the elements to be processed in accordance with said operation result under the control of said control means and transferring the selected element to said memory means.
Claim 8
Dependent Claim
53 words
A vector processing apparatus according to Claim 6 wherein said address control means includes address register means (200 and 201) for reading out the elements of the vector operands and update means (203, 204) for controlling updating of said address register means in accordance with said operation result supplied from said control means.
Claim 9
Dependent Claim
104 words
A vector processing apparatus according to Claim 4 wherein each of the elements of the vector operands comprises a first part for representing a numeric data and a second part for identifying said numeric data, and said vector processing means includes first compare means (1713) for comparing the elements of two vector operands, second compare means (1714, 1715) for comparing adjacent elements in each operand, and means (1716, 1717) for combining the identification information of the elements having the same numeric data in accordance with the compare results of said first and second compare means and transferring the combined information to said memory means.
References Cited (Backward Citations)
No citation records indexed.
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