Multicomputer digital processing system

Claim 2

A data processing system comprising: a first information bus means for the transfer of information between a plurality of a first group of devices connected thereto; at least one second information bus means for the transfer of information between a second group of devices connected thereto; a bus interface means for providing information transfers between said first and said second information bus means; said second information bus means including an interface means connected thereto for responding to information transfers and providing status information of the first group or the second group devices, and further connected to a Lock Bus for transmitting requests for access to individual devices and for receiving grants of such requests, said Lock Bus connected to a lock arbitration means for receiving the request and for providing grants to access the individual devices in accordance with a predetermined arbitration scheme.

Claim 3

A data processing system comprising: A. a first information bus means for the transfer of information including address, data, control and interrupt information between a first group of devices connected thereto; B. at least one second information bus means for the transfer of information including address, data, control and interrupt information between a second group of devices connected thereto; C. an information bus interface means connecting the first information bus with the second information bus and providing for transfer of information between the first group and second group of devices; and D. interrupt control logic connected to said first information bus means and including; (1) interrupt control access decode means for receiving address information from the first bus and determining when an information transfer is intended for the interrupt control logic, generating a signal when such a transfer is received; (2) an interrupt word register means for receiving the indication from the decode means and selecting one of a plurality of registers in accordance with the received address, each register dedicated to particular one of either the first group or second group of devices and either, ORing the contents of the selected register with the information transfer data in the register for a write operation, or clearing the contents of the register after a read operation; (3) interrupt generation means for receiving said indication from the interrupt address decoder means and, for a write operation, generating a interrupt signal to the register's device; and (4) an interrupt response logic means to generate response signals to the information transfer.

Claim 4

A data processing system comprising: A. a first information bus means for the transfer of information including address, data, control and interrupt information between a first group of devices connected thereto; B. at least one second information bus means for the transfer of information including address, data, control and interrupt information between a second group of devices connected thereto; C. an information bus interface means connecting the first information bus with the second information bus and providing for transfer of information between the first group and second group of devices; and D. interrupt control logic connected to said first information bus means and including; (1) interrupt control access decode means for receiving address information from the first bus and determining when an information transfer is intended for the interrupt control logic, generating a signal when such a transfer is received; (2) an interrupt word register means for receiving the indication from the decode means and selecting one of a plurality of registers in accordance with the received address, each register dedicated to particular one of either the first group or second group of devices and either, ORing the contents of the selected register with the information transfer data in the register for a write operation, or clearing the contents of the register after a read operation; (3) interrupt generation means for receiving said indication from the interrupt address decoder means and, for a write operation, generating a interrupt signal to the register's device; and (4) an interrupt response logic means to generate response signals to the information transfer.

Claim 5

A data processing system comprising: A. a first information bus means for the transfer of information including address, data, control and interrupt information, said transfer in accordance with a first protocol defining procedures, timing and formats for exchange of information between a requestor and a responder among a plurality of devices connected thereto; B. at least one second information bus means for the transfer of information including address, data, control and interrupt information, said transfer in accordance with a second protocol. defining procedures, timing and formats for an exchange between a requestor device and a responder device among a plurality of devices connected thereto; C. an information bus interface means connecting said first information bus to said second information bus and providing for the transfer of information between devices connected to either information buses;

Claim 6

A data processing system comprising: A. a first information bus means for the transfer of information including address, data, control and interrupt information, said transfer in accordance with a first protocol defining procedures, timing and formats for exchange of information between a requestor and a responder among a plurality of devices connected thereto; B. at least one second information bus means for the transfer of information including address, data, control and interrupt information, said transfer in accordance with a second protocol. defining procedures, timing and formats for an exchange between a requestor device and a responder device among a plurality of devices connected thereto; C. an information bus interface means connecting said first information bus to said second information bus and providing for the transfer of information between devices connected to either information buses;

Claim 7

D. a memory connected to said first information bus means and including; (1) a memory address decode means for decoding received address information and, accordingly, generating a signal indicating that the information on the first information bus means is to be transferred to the memory; (2) memory interface logic means for receiving the indication signal from the decoding means and generating access signals to a memory unit providing access to the memory unit in accordance with said first bus protocol; (3) memory response logic means for generating a response on the first information bus means responding to the information transfer.

Claim 8

D. a memory connected to said first information bus means and including; (1) a memory address decode means for decoding received address information and, accordingly, generating a signal indicating that the information on the first information bus means is to be transferred to the memory; (2) memory interface logic means for receiving the indication signal from the decoding means and generating access signals to a memory unit providing access to the memory unit in accordance with said first bus protocol; (3) memory response logic means for generating a response on the first information bus means responding to the information transfer.

Claim 9

A data processing system including: A. a first information bus means for the transfer of information including address, data, control and interrupt information in accordance with a first protocol defining procedures, timing and formats for an exchange between devices connected thereto; B. at least one second information bus means for the transfer of information including address, data, control and interrupt information in accordance with a second protocol defining procedures, timing and formats for an exchange between a second group of devices connected thereto; C. an information bus interface means providing for the transfer of information between devices connected to either information bus and further including bus access arbitration means including a requestor means for receiving a signal indicating a request to access one information bus means from the other information bus means and for transmitting said request and receiving a grant indication, upon receiving the grant indication providing for the information transfer between the two information bus means; and D. an arbitration means connected to receive the request for access and for providing request grants in accordance with a predetermined arbitration scheme.

Claim 10

A data processing system including: A. a first information bus means for the transfer of information including address, data, control and interrupt information in accordance with a first protocol defining procedures, timing and formats for an exchange between devices connected thereto; B. at least one second information bus means for the transfer of information including address, data, control and interrupt information in accordance with a second protocol defining procedures, timing and formats for an exchange between a second group of devices connected thereto; C. an information bus interface means providing for the transfer of information between devices connected to either information bus and further including bus access arbitration means including a requestor means for receiving a signal indicating a request to access one information bus means from the other information bus means and for transmitting said request and receiving a grant indication, upon receiving the grant indication providing for the information transfer between the two information bus means; and D. an arbitration means connected to receive the request for access and for providing request grants in accordance with a predetermined arbitration scheme.

Claim 11

A timing distribution device connectable to a plurality of timed devices of an information bus and including separate timing lines connected to the timing device, said timing device including individual propagation path lines matched to propagation path timing lines of the information bus wherein single timing pulses from an oscillator on the timing device are received approximately at the same time by each of the timed devices.

Claim 12

A timing distribution device connectable to a plurality of timed devices of an information bus and including separate timing lines connected to the timing device, said timing device including individual propagation path lines matched to propagation path timing lines of the information bus wherein single timing pulses from an oscillator on the timing device are received approximately at the same time by each of the timed devices.

Claim 13

A computer unit comprising: A. a Resource Monitor connected to an External Bus for controlling and monitoring the computer unit circuitry; B. a processor for independently executing instructions on data connected to the Resource Monitor and an Internal Bus and further including an address decode circuit connected to receive a processor address space from the Resource Monitor and for providing an indication when the processor is being addressed by a transfer on the Internal Bus; C. a computer clock means for providing at least one timing signal to the computer unit circuitry; D. bus address decoding means for decoding addresses received from a first and a second information bus and indicating when the computer unit is being addressed from either bus, and providing an indication of such access; E. bus interface means connected to the Internal Bus, the first information bus and the second information bus and storing address translation information from the Resource Monitor for providing a translated address to the Internal Bus in response to an address received from the second information bus and further providing the transfer of information between said Internal Bus and either said first information bus or said second information bus and providing an information transfer between said first information bus and said second information bus; F. bus request means for receiving signals from said processor or one of said information buses indicating a request for the other of said information buses and transmitting the request upon a Resource Monitor designated line to an arbitration circuit which provides a grant of access in accordance with a Resource Monitor selected one of a plurality of arbitration schemes, said plurality provided by said Resource Monitor; G. access control means for providing control signals to regulate the transfer of information between the processor, a memory, the first information bus and the second information bus with said Internal Bus; H. the memory provided for storage of information and connected to the Internal Bus and including a memory control means connected to receive control signals from the access control means for enabling information to be read from and written to the memory via the Internal Bus.

Claim 14

A computer unit comprising: A. a Resource Monitor connected to an External Bus for controlling and monitoring the computer unit circuitry; B. a processor for independently executing instructions on data connected to the Resource Monitor and an Internal Bus and further including an address decode circuit connected to receive a processor address space from the Resource Monitor and for providing an indication when the processor is being addressed by a transfer on the Internal Bus; C. a computer clock means for providing at least one timing signal to the computer unit circuitry; D. bus address decoding means for decoding addresses received from a first and a second information bus and indicating when the computer unit is being addressed from either bus, and providing an indication of such access; E. bus interface means connected to the Internal Bus, the first information bus and the second information bus and storing address translation information from the Resource Monitor for providing a translated address to the Internal Bus in response to an address received from the second information bus and further providing the transfer of information between said Internal Bus and either said first information bus or said second information bus and providing an information transfer between said first information bus and said second information bus; F. bus request means for receiving signals from said processor or one of said information buses indicating a request for the other of said information buses and transmitting the request upon a Resource Monitor designated line to an arbitration circuit which provides a grant of access in accordance with a Resource Monitor selected one of a plurality of arbitration schemes, said plurality provided by said Resource Monitor; G. access control means for providing control signals to regulate the transfer of information between the processor, a memory, the first information bus and the second information bus with said Internal Bus; H. the memory provided for storage of information and connected to the Internal Bus and including a memory control means connected to receive control signals from the access control means for enabling information to be read from and written to the memory via the Internal Bus.

Claim 15

An information bus interface circuit for providing for the transfer of information between a first information bus and a second information bus, said circuit comprising: A. a bus requestor means for receiving a signal indicating a request for access from one of the two buses and for transmitting the request to an external arbiter and receiving a grant indication from said arbiter; B. a bus address decode means for receiving bus signals including bus addresses and comparing the received address with a preprogrammed address space, determining when the received addresses within the preprogrammed address space and accordingly generating a signal indicating that the information present on one bus is to be transferred to the other bus; C. a first/second bus transfer means for transferring information from a plurality of first bus signal lines to a plurality of second bus signal lines in accordance with received control signals; D. protocol signal control logic means for, in response to information on one of the information buses, receiving said indication from the bus address decode means, and in accordance with such indication, transmitting a request to the bus requestor means, generating control signals to the first/second bus transfer means for the transfer of the information, and generating a response on the one bus to complete the information transfer.

Claim 16

An information bus interface circuit for providing for the transfer of information between a first information bus and a second information bus, said circuit comprising: A. a bus requestor means for receiving a signal indicating a request for access from one of the two buses and for transmitting the request to an external arbiter and receiving a grant indication from said arbiter; B. a bus address decode means for receiving bus signals including bus addresses and comparing the received address with a preprogrammed address space, determining when the received addresses within the preprogrammed address space and accordingly generating a signal indicating that the information present on one bus is to be transferred to the other bus; C. a first/second bus transfer means for transferring information from a plurality of first bus signal lines to a plurality of second bus signal lines in accordance with received control signals; D. protocol signal control logic means for, in response to information on one of the information buses, receiving said indication from the bus address decode means, and in accordance with such indication, transmitting a request to the bus requestor means, generating control signals to the first/second bus transfer means for the transfer of the information, and generating a response on the one bus to complete the information transfer.

Claim 17

A data processing system comprising: A. a plurality of processing units, each processing unit connected to a first information bus, said information bus including a plurality of signal lines for the transfer of address data, control and interrupt information, said processing units including address decode circuitry for determining when an address on the information bus is within a address space allotted to the processing device, each processing device further including a monitor circuit connected to a programmable portion of the decoding means for providing the processing unit address space, said monitor circuits connected to one another by a second serial information bus and further connected to a system monitor means for providing each of the processing devices with a unique address space via the second information bus.

Claim 18

A data processing system comprising: A. a plurality of processing units, each processing unit connected to a first information bus, said information bus including a plurality of signal lines for the transfer of address data, control and interrupt information, said processing units including address decode circuitry for determining when an address on the information bus is within a address space allotted to the processing device, each processing device further including a monitor circuit connected to a programmable portion of the decoding means for providing the processing unit address space, said monitor circuits connected to one another by a second serial information bus and further connected to a system monitor means for providing each of the processing devices with a unique address space via the second information bus.

Claim 19

A data processing system comprising: A. a first information bus for the transfer of address, data and control information and including a plurality of signal lines; B. a second information bus for the transfer of address, data and control information and including a second plurality of signal lines; C. a plurality of bus interface devices each connecting one of said second information buses to the first information bus and providing for the information transfer between the first and second information buses; D. a plurality of computational devices connected to said second information buses, each computational device being addressably accessible by any other computational device, said computational devices including bus transfer means for transferring information over the first and second information buses to other computational devices, said bus transfer means further including a bus request circuit for sending request for access to the Second information bus to an arbitration circuit for granting access to the second information bus, each of said computational devices including a monitor circuit connected to control the bus request circuit and further connected to store information in a programmable portion of the arbitration circuit that determines which of the received request is granted access, said monitor circuits connected by a serial bus to a system monitor means for configuring the bus request circuits and the arbitration circuit.

Claim 20

A data processing system comprising: A. a first information bus for the transfer of address, data and control information and including a plurality of signal lines; B. a second information bus for the transfer of address, data and control information and including a second plurality of signal lines; C. a plurality of bus interface devices each connecting one of said second information buses to the first information bus and providing for the information transfer between the first and second information buses; D. a plurality of computational devices connected to said second information buses, each computational device being addressably accessible by any other computational device, said computational devices including bus transfer means for transferring information over the first and second information buses to other computational devices, said bus transfer means further including a bus request circuit for sending request for access to the Second information bus to an arbitration circuit for granting access to the second information bus, each of said computational devices including a monitor circuit connected to control the bus request circuit and further connected to store information in a programmable portion of the arbitration circuit that determines which of the received request is granted access, said monitor circuits connected by a serial bus to a system monitor means for configuring the bus request circuits and the arbitration circuit.

Claim 21

An information bus control unit connectable to a first bus and a second bus comprising: (1) circuit means for transferring information between the first bus and the second bus in accordance with the first bus and second bus protocols; and (2) interrupt control means connected to the first bus and including addressable registers for storing of interrupt status information for each interruptable unit of the system and for generating signals to these interruptable units when data is stored in these registers.

Claim 22

An information bus control unit connectable to a first bus and a second bus comprising: (1) circuit means for transferring information between the first bus and the second bus in accordance with the first bus and second bus protocols; and (2) interrupt control means connected to the first bus and including addressable registers for storing of interrupt status information for each interruptable unit of the system and for generating signals to these interruptable units when data is stored in these registers.

Claim 23

An Information Bus access unit connectable to a first bus and a second bus comprising: (1) a memory connected to and responding to information transfers from the first bus and; (2) circuit means for transferring information between the first bus and the second bus in accordance with first bus and second bus protocols.

Claim 24

An Information Bus access unit connectable to a first bus and a second bus comprising: (1) a memory connected to and responding to information transfers from the first bus and; (2) circuit means for transferring information between the first bus and the second bus in accordance with first bus and second bus protocols.

Claim 25

A data processing system comprising: a first bus; at least two second buses, each second bus connectable to at least one device means for accessing information; and each second bus connected to a bus interface means for transferring information between the first and second buses and for providing a first bus transfer rate at least equal to a second bus transfer rate.

Claim 26

A data processing system comprising: a first bus; at least two second buses, each second bus connectable to at least one device means for accessing information; and each second bus connected to a bus interface means for transferring information between the first and second buses and for providing a first bus transfer rate at least equal to a second bus transfer rate.

Claim 27

A data processing system comprising: a first bus; at least two second buses, each second bus connectable to at least one device means for accessing information with the second bus, at least one device means further including a third bus interface means for providing a transfer of information between said device means and a third bus; and each second bus means connected to a first bus interface means for transferring information between the first and second buses.

Claim 28

A data processing system comprising: a first bus; at least two second buses, each second bus connectable to at least one device means for accessing information with the second bus, at least one device means further including a third bus interface means for providing a transfer of information between said device means and a third bus; and each second bus means connected to a first bus interface means for transferring information between the first and second buses.

Claim 29

A data processing system comprising: an information bus for transferring information between at least two devices connected to the bus and in accordance with a bus protocol including an override signal for responding to a requesting device and causing the requesting device to cease any information transmissions.

Claim 30

A data processing system comprising: an information bus for transferring information between at least two devices connected to the bus and in accordance with a bus protocol including an override signal for responding to a requesting device and causing the requesting device to cease any information transmissions.

Claim 31

A data processing system comprising: an information bus for the transfer of information between at least two devices in accordance with a bus protocol including an interlock signal from a requesting device to a responding device causing the responding device to only perform information transfers with the requesting device until released by the requesting device.

Claim 32

A data processing system comprising: an information bus for the transfer of information between at least two devices in accordance with a bus protocol including an interlock signal from a requesting device to a responding device causing the responding device to only perform information transfers with the requesting device until released by the requesting device.

Claim 33

A data processing system comprising: an information bus for a transfer of information between at least two devices and in accordance with a bus protocol including a wait signal for transmission by a responding device to a requesting device and causing the requesting device to monitor the bus for the occurrence of predetermined data before completing information transfers with devices other than the responding device.

Claim 34

A data processing system comprising: an information bus for a transfer of information between at least two devices and in accordance with a bus protocol including a wait signal for transmission by a responding device to a requesting device and causing the requesting device to monitor the bus for the occurrence of predetermined data before completing information transfers with devices other than the responding device.

Claim 35

A data processing system comprising: a first bus; at least two second buses, each second bus connectable to at least one device means for accessing information; and each second bus connected to a bus interface means for transferring information between the first and second buses; and including at least one memory device directly addressable by devices connected to either bus.

Claim 36

A data processing system comprising: a first bus; at least two second buses, each second bus connectable to at least one device means for accessing information; and each second bus connected to a bus interface means for transferring information between the first and second buses; and including at least one memory device directly addressable by devices connected to either bus.

Claim 37

A data processing system comprising: a first bus; at least two second buses, each second bus connectable to at least one device means for accessing information; and each second bus connected to a bus interface means for transferring information between the first and second buses and further an arbitration means for resolving contention between multiples of attempted transfers between said second buses and said first bus.

Claim 38

A data processing system comprising: a first bus; at least two second buses, each second bus connectable to at least one device means for accessing information; and each second bus connected to a bus interface means for transferring information between the first and second buses and further an arbitration means for resolving contention between multiples of attempted transfers between said second buses and said first bus.

Claim 39

A data processing system comprising: a first bus; at least four second buses, each second bus connectable to at least one device means for accessing information; and each second bus connected to a bus interface means for transferring information between the first and second buses and said first bus further including redundant information paths and said interface means further provides for transfer of information over said redundant information paths simultaneously.

Claim 40

A data processing system comprising: a first bus; at least four second buses, each second bus connectable to at least one device means for accessing information; and each second bus connected to a bus interface means for transferring information between the first and second buses and said first bus further including redundant information paths and said interface means further provides for transfer of information over said redundant information paths simultaneously.

Claim 41

A data processing system comprising: an information bus for transfer of information between at least two devices and further including a single interrupt means directly addressable via the information bus and for providing interrupts to selected devices.

Claim 42

A data processing system comprising: an information bus for transfer of information between at least two devices and further including a single interrupt means directly addressable via the information bus and for providing interrupts to selected devices.

Claim 43

A data processing system comprising: an information bus for a transfer of information between at least two devices and including a lock means addressable via the information bus for providing the status of the devices connected to the bus.

Claim 44

A data processing system comprising: an information bus for a transfer of information between at least two devices and including a lock means addressable via the information bus for providing the status of the devices connected to the bus.

Claim 45

An electronic assembly comprising: a connector including a first plurality of pins mounted in a similar direction and a second plurality of pins mounted in relationship with the first plurality of pins, said second plurality of pins having a greater height than the first plurality of pins, and further connected to a power source; and a card assembly having a connector assembly for mating with the connector and including circuitry to provide a first indication upon the mating of the second plurality of pins with the connector assembly and providing a second indication indicating the attainment of a specific voltage level within the circuitry on the card assembly.

Claim 46

An electronic assembly comprising: a connector including a first plurality of pins mounted in a similar direction and a second plurality of pins mounted in relationship with the first plurality of pins, said second plurality of pins having a greater height than the first plurality of pins, and further connected to a power source; and a card assembly having a connector assembly for mating with the connector and including circuitry to provide a first indication upon the mating of the second plurality of pins with the connector assembly and providing a second indication indicating the attainment of a specific voltage level within the circuitry on the card assembly.

Claim 47

A data processing system comprising: a housing including a first bus connected to a plurality of first bus connectors and at least two second buses, each second bus having an individual plurality of second bus connectors, each of said second buses positioned approximately orthogonally with said first bus and each of said first bus connectors positioned in a relationship with one of the second bus plurality of connectors; at least one bus interface card means for connecting between one of said first bus connectors and said second bus connectors and for providing a transfer of information between the connected second bus and the first bus; and a processor card means plugably connected to said second bus connectors for processing information, accessing information on the second bus, for initiating information transfers from said second bus through said bus interface means to the first bus for communicating with other devices, and for responding to information transfers received on the second bus.

Claim 48

A data processing system comprising: a housing including a first bus connected to a plurality of first bus connectors and at least two second buses, each second bus having an individual plurality of second bus connectors, each of said second buses positioned approximately orthogonally with said first bus and each of said first bus connectors positioned in a relationship with one of the second bus plurality of connectors; at least one bus interface card means for connecting between one of said first bus connectors and said second bus connectors and for providing a transfer of information between the connected second bus and the first bus; and a processor card means plugably connected to said second bus connectors for processing information, accessing information on the second bus, for initiating information transfers from said second bus through said bus interface means to the first bus for communicating with other devices, and for responding to information transfers received on the second bus.

Claim 49

A data processing system comprising: a first information transfer bus; at least two second information transfer buses each connected to the first bus through a bus interface means for transferring information between the first and second buses, said bus interface means controlling first bus information transfers in accordance with a first bus protocol; at least one processing means each connectable to said second buses for processing information and for transferring information over said buses; a memory means for storing information and addressable via said buses; an interrupt means addressable via said buses and for providing interrupt signals; a monitor means for monitoring the buses, and for monitoring and controlling the bus interface means, the processing means, the memory means and the interrupt means and connected to a third information bus; and a system monitor means connected to said third information bus for providing information to said monitor means.

Claim 50

A data processing system comprising: a first information transfer bus; at least two second information transfer buses each connected to the first bus through a bus interface means for transferring information between the first and second buses, said bus interface means controlling first bus information transfers in accordance with a first bus protocol; at least one processing means each connectable to said second buses for processing information and for transferring information over said buses; a memory means for storing information and addressable via said buses; an interrupt means addressable via said buses and for providing interrupt signals; a monitor means for monitoring the buses, and for monitoring and controlling the bus interface means, the processing means, the memory means and the interrupt means and connected to a third information bus; and a system monitor means connected to said third information bus for providing information to said monitor means.