EP0184397A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Real-time software monitor and write protect controller
Assignee: Honeywell Inc
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Filing: 1985-11-29
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Granted: —
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Expires: 2005-11-29
Abstract
Abstract Verification of proper operation of computer programs executing in a central processor and protection of critical data is accomplished by an independent software monitor (10) which accepts data keys from the executing program and ouputs defined legitimate codes in response thereto. Legitimate codes and selected portions of input data keys are compared (12) to validate proper software execution.
Inventors
- 👤 Larry James Yount
- 👤 Bryan Harris Hill
- 👤 Nicholas John Wilt
- 👤 Donald Arthur Peterson, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 06:12
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/14; G06F12/1458; G06F12/1466; G06F11/00; G06F11/28; G06F11/07; G06F11/0703; G06F11/0751; G06F11/0763
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
117 words
Real-time software monitor and write protect apparatus, characterised in that it comprises means (10) for providing a sequence of memory addresses in response to the input of a sequence of data keys, said data keys occurring at selected times during execution of a program in a central processor, means (11) for sequentially accepting the memory addresses and providing in response thereto a plurality of sequential legitimate codes, means (12) for sequentially comparing the legitimate codes with selected portions of the data keys to provide therefrom a signal indicating the validity of the keys, and means for providing software isolation by specifying areas of memory that may not be altered in response to the sequence of data keys.
Claim 2
Dependent Claim
117 words
Real-time software monitor and write protect apparatus, characterised in that it comprises means (10) for providing a sequence of memory addresses in response to the input of a sequence of data keys, said data keys occurring at selected times during execution of a program in a central processor, means (11) for sequentially accepting the memory addresses and providing in response thereto a plurality of sequential legitimate codes, means (12) for sequentially comparing the legitimate codes with selected portions of the data keys to provide therefrom a signal indicating the validity of the keys, and means for providing software isolation by specifying areas of memory that may not be altered in response to the sequence of data keys.
Claim 3
Dependent Claim
72 words
Apparatus as recited in claim 1, characterised in that it further comprises means (18) for providing a signal indicating the occurrence of a last data key in the sequence of data keys, means (27) for providing a signal indicating valid completion of a sequence of data keys in response to receipt of the signal indicating validity of data keys and the signal indicating occurrence of the last data key in a sequence.
Claim 4
Dependent Claim
68 words
Apparatus as recited in claim 1 or 2, characterised in that it further comprises means (15) for timing the duration of a software task and for providing a signal representative of an end-of-task occurrence, and means (28) for providing a signal indicating the valid execution software task based on a mutual occurrence of the end-of-task signal and the signal indicating valid completion of a sequence of data keys.
Claim 5
Dependent Claim
79 words
Apparatus as recited in any of the preceding claims, characterised in that it further comprises means (34) for providing a signal designating a selected software task from a plurality of software tasks, the task-select signal becoming part of the sequence of memory addresses, and for providing a control code in response to the input of the sequence of data keys, and means (44) responsive to the control code for providing a signal indicating the validity of the control code.
References Cited (Backward Citations)
No citation records indexed.
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