EP0183550A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Compound semiconductor device
Assignee: Fujitsu Ltd
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Filing: 1985-11-28
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Granted: —
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Expires: 2005-11-28
Abstract
Abstract An IC device comprising a plurality of FET's (26, 27, 28, 29) using a compound semiconductor, more specifically, a zincblende type semiconductor substrate (25), having a surface of a (111) plane. By use of this plane, differences of characteristics of the FET's depending on directions along which gates (27) of the FET's are arranged when the gate length is made shorter are prevented, allowing arrangement of gates of the FET's different directions, particularly perpendicular to each other, and allowing the gate length to be made shorter to miniaturize and densify the device.
Inventors
- 👤 Tsukasa Onodera
- 👤 Haruo Kawata
- 👤 Toshiro Futatsugi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 15:16
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/80; H10D62/86; H10D62/8603; H10D48/00; H10D48/50; H10D62/40; H10D62/405; H10D62/85; H10D62/852; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0158; H10D84/0165; H10D84/0193
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
31 words
A semiconductor device, comprising: a zincblende type compound semiconductor substrate having a surface of a (111) plane and a plurality of field effect transistors (FET's) formed in and on said substrate.
Claim 2
Dependent Claim
31 words
A semiconductor device, comprising: a zincblende type compound semiconductor substrate having a surface of a (111) plane and a plurality of field effect transistors (FET's) formed in and on said substrate.
Claim 3
Dependent Claim
15 words
A device according to claim 1, wherein said substrate is of a III-V compound semiconductor.
Claim 4
Dependent Claim
33 words
A device according to claim 2, wherein said III-V compound semiconductor is selected from the group consisting of GaAs, InP, InSb, GaP, AlSb, BN, BP, AlAs, InGaAsP, AlGaAsP, InGaAsSb, AlGaAsSb, AlGaInP, and AlGaAsSb.
Claim 5
Dependent Claim
15 words
A device according to claim 1, wherein said substrate is of a II-VI compound semiconductor.
Claim 6
Dependent Claim
37 words
any preceding 5. A device according to any preceding claim, wherein said comprise FET's / one or more of the group consisting of a MESFET, a JFET, a MISFET, and a two-dimensional carrier gas channel type FET.
Claim 7
Independent Claim
56 words
A device according to any preceding claim, said FET's comprising source and drain regions in said substrate, a channel region in said substrate between the source and drain regions, and a gate electrode over the channel region, wherein the gates of said FET's are arranged in two or more directions on the surface of said substrate.
Claim 8
Dependent Claim
18 words
A device according to claim 6, wherein said device includes FET's having gates arranged perpendicular to each other.
Claim 9
Dependent Claim
20 words
A device according to claim 6, wherein said gates are arranged along [112] and [110] axes on the (111) plane.
Claim 10
Independent Claim
75 words
A device according any of claims/said FET's comprising source and drain regions in said substrate, a channel region in said substrate between the source and drain regions, a gate electrode over the channel region, and an insulating layer over the substrate, wherein said gate electrode.and said insulating layer are made in such a manner that said gate electrode and said insulating layer induce piezoelectric charge in said substrate which reduces leakage current through the substrate.
Claim 11
Dependent Claim
49 words
A device according to claim 9, wherein said FET's are an n-channel type, said substrate has a surface of a (lll)A plane, and said gate electrode and said insulating layer induce tensile stress to said substrate including said channel region, whereby the concentration of n-type majority carriers is reduced.
Claim 12
Dependent Claim
18 words
9 or 11. A device according to claim/10, wherein said insulating layer is of silicon dioxide. 10or 11
Claim 13
Dependent Claim
48 words
A device according to claim 9,/wherein said FET's are a p-channel type, said substrate has a surface of a (lll)A plane, and said gate electrode and said insulating layer induce compressive stress to said substrate including said channel region, whereby the concentration of p-type majority carrier is reduced.
Claim 14
Dependent Claim
26 words
9 or 10, or clam 12 except when appended to claim 11. 13. A device according to claim, wherein said insulating layer is of silicon nitride.
Claim 15
Dependent Claim
49 words
A device according to claim 9, wherein said FET's are an n-channel type, said substrate has a surface of a (lll)B plane, and said gate electrode and said insulating layer induce compressive stress to said substrate insulating said channel region, whereby the concentration of n-type majority carriers is reduced.
Claim 16
Dependent Claim
14 words
A device according to claim 14, wherein said insulating layer is of silicon nitride.
Claim 17
Dependent Claim
49 words
A device according to claim 9, wherein said FET's are a p-channel type, said substrate has a surface of a (lll)B plane, and said gate electrode and said insulating layer induce tensile stress to said substrate insulating said channel region, whereby the concentration of p-type majority carriers is reduced.
Claim 18
Dependent Claim
14 words
A device according to claim 16, wherein said insulating layer is of silicon dioxide.
Claim 19
Dependent Claim
71 words
A device according to claim 9, wherein said FET's are complementary n- and p-channel type, said substrate has a surface of a (lll)A plane, and said gate electrode and said insulating layer induce tensile stress to a part of said substrate including said n-type channel region and compressive stress to a part of said substrate including said p-type channel region, whereby the concentrations of n-type and p-type majority carriers are reduced.
Claim 20
Dependent Claim
71 words
A device according to claim 9, wherein said FET's are complementary n- and p-channel type, said substrate has a surface of a (lll)B plane, and said gate electrode and said insulating layer induce compressive stress to a part of said substrate including said n-type channel region and tensile stress to a part of said substrate including said p-type channel region, whereby the concentrations of n-type and p-type majority carriers are reduced.
Claim 21
Independent Claim
21 words
A device according to any preceding claim, wherein the length of said gate of said FET's is 2 um or less.
References Cited (Backward Citations)
No citation records indexed.
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