Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
97 words
A semiconductor integrated circuit device comprising: an information processing circuit (1) adapted to be operated by a periodic timing signal; a memory (2, 20a-h) including a memory array and a peripheral circuit (10, 22, 23, 24, 25) adapted to be statically and dynamically operated to access the former; and a control circuit (27) for statically operating said peripheral circuit, when said memory is to be controlled directly from the outside, and for dynamically operating said peripheral circuit on the basis of said timing signal when said memory is to be controlled by said information processing circuit (1).
Claim 2
Dependent Claim
97 words
A semiconductor integrated circuit device comprising: an information processing circuit (1) adapted to be operated by a periodic timing signal; a memory (2, 20a-h) including a memory array and a peripheral circuit (10, 22, 23, 24, 25) adapted to be statically and dynamically operated to access the former; and a control circuit (27) for statically operating said peripheral circuit, when said memory is to be controlled directly from the outside, and for dynamically operating said peripheral circuit on the basis of said timing signal when said memory is to be controlled by said information processing circuit (1).
Claim 3
Dependent Claim
25 words
A semiconductor integrated circuit device according to claim 1, wherein said memory array (2) includes a plurality of erasably programmable semiconductor nonvolatile memory elements (MC).
Claim 4
Dependent Claim
82 words
A semiconductor integrated circuit device according to claim 1, wherein said peripheral circuit includes a read circuit (25) having: a sense amplifier (54) made receptive to a data signal from said memory array; and a latch circuit (34) made receptive to the output of said sense amplifier (54) , and wherein said control circuit (27) is operative to output a control signal for interrupting the operation current of said sense amplifier (54) after read data has been latched by said latch circuit.
Claim 5
Dependent Claim
52 words
A semiconductor integrated circuit device according to claim 1, further comprising: a dummy memory array (21); and a read circuit (26) for said dummy memory array, and wherein said control circuit (27) is responsive to the output of said read circuit (26) to output a control signal for said peripheral circuit (22-25).
Claim 6
Dependent Claim
27 words
A semiconductor integrated circuit divice according to claim 1, wherein said peripheral circuit includes an address decoder (22) adapted to be dynamically operated by said timing signal.
Claim 7
Dependent Claim
99 words
A semiconductor integrated circuit device according to claim 5, wherein said address decoder (22) includes: a first MOSFET (Q ) connected between one of the terminals of a power supply (Vcc) and an output node (n 1 ) for feeding said output node with either a charge for the dynamic operation or an operation current for the static operation; and a plurality of second MOSFETs (Qd1 ... Qd4) connected in series between said output node (n 1 ) and the other terminal of said power supply for being switched by respective address signals (A 1 ... A 7 ).