EP0182353A2 — Random access memory device formed on a semicondu…

Claim 1

Independent Claim 267 words

A dynamic random access memory device (DRAM) formed on a semiconductor substrate having an array of dynamic memory cells (MC) arranged in a matrix, said array being devided into a plurality of sub-arrays (subsections) (10 - 13) of said memory cells (MC) characterized in a plurality of memory blocks each including one of said sub-arrays (10-13) and the associated peripheral means therewith; an access peripheral circuit (30) for outputting access address signals (AAi) for access operation, said access address signals (AAi) being used partially for selecting one of said memory blocks, and partially for accessing one of said memory cells (MC) of said sub-array (10-13) contained in said memory block thus selected; a refresh peripheral circuit (20) for outputting refresh address signals (RAi) for refreshing operation, said refresh address signals (RAi) being used partially for selecting one of said memory blocks and partially for refreshing said memory cells (MC) of said memory block thus selected sequentially and cyclically according to a predetermined refresh timing schedule; and a block selection peripheral circuit (40) for detecting a double selection, namely simultaneous selection of the same memory block for said access operation and said refresh operation, for selectively implementing said access operation and said refresh operation; whereby, whennone of said double selection is detected, said refresh operation and said access operation are allowed to be performed in parallel, and when said double selection ist detected the preferantial implementation of said refresh operation or said access operation is performed according to a predetermined schedule of priority to one of both operations under the control of said block selection peripheral circuit (40).

Claim 2

Dependent Claim 267 words

A dynamic random access memory device (DRAM) formed on a semiconductor substrate having an array of dynamic memory cells (MC) arranged in a matrix, said array being devided into a plurality of sub-arrays (subsections) (10 - 13) of said memory cells (MC) characterized in a plurality of memory blocks each including one of said sub-arrays (10-13) and the associated peripheral means therewith; an access peripheral circuit (30) for outputting access address signals (AAi) for access operation, said access address signals (AAi) being used partially for selecting one of said memory blocks, and partially for accessing one of said memory cells (MC) of said sub-array (10-13) contained in said memory block thus selected; a refresh peripheral circuit (20) for outputting refresh address signals (RAi) for refreshing operation, said refresh address signals (RAi) being used partially for selecting one of said memory blocks and partially for refreshing said memory cells (MC) of said memory block thus selected sequentially and cyclically according to a predetermined refresh timing schedule; and a block selection peripheral circuit (40) for detecting a double selection, namely simultaneous selection of the same memory block for said access operation and said refresh operation, for selectively implementing said access operation and said refresh operation; whereby, whennone of said double selection is detected, said refresh operation and said access operation are allowed to be performed in parallel, and when said double selection ist detected the preferantial implementation of said refresh operation or said access operation is performed according to a predetermined schedule of priority to one of both operations under the control of said block selection peripheral circuit (40).

Claim 3

Dependent Claim 165 words

A dynamic random access memory device (DRAM) according to claim 1, characterized in that said block selection peripheral circuit (40) comprises: a first decoder (41) outputting refresh block selection signals (RBS0..3) by decoding inputted said refresh signals (RA9, RA10); a second decoder (42) outputting access block selection signals (PABS0..3) by decoding inputted said access signals (AA9, AA10); a comparison circuit (43) for detecting said double selection of the same memory block by comparing said access block selection signals (PABS0..3) with said refresh block selection signals (RBS0..3) and outputting a double selection signal (EQ) when said double selection is detected; and an access signal invalid circuit (45), receiving said access block selection signals and said double selection signal (EQ), and selectively invalidating said access block selection signals, such that said access block selection signals are allowed to be outputted when no said double selection is detected, and are invalidated when said double selection is detected, thus, said refresh operation is preferentially performed over said access operation.

Claim 4

Dependent Claim 245 words

A dynamic random access memory device (DRAM) according to claim 1, characterized in that said block selection peripheral circuit (40) comprises; a first decoder (41) outputting refresh block selection signals (PRBS0...3) by decoding inputted said refresh signals (RA9, RA10); a second decoder (42) outputting access block selection signals (PABS0..3) by decoding inputted said access signals (AA9, AA10); a comparison circuit (43) for detecting said double selection of the same memory block by comparing said access block selection signals (PABS0..3) with refresh block selection signals (PRBS0..3), and outputting a double selection signal (EQ) when said double selection is detected; a refresh signal invalid circuit (47) for receiving said refresh block selection signals (PRBS0..3) and said double selection signal (EQ) and selectively invalidating said access block selection signals; an access signal invalid circuit (45) for receiving said access block selection signals(PABS 0..3) and said double selection signal (EQ) and selectively invalidating said refresh block selection signals; and a priority providing means (46, 48) having a predetermined priority schedule stored thereinside, such that when said double selection signal (EQ) is sent from said comparison circuit (43) to said priority providing means (46, 48), one of said refresh operation and said access operation is preferentially implemented by invalidating one of a group of said access block selection signals and a group of said refresh block selection signals according to said predetermined priority schedule, and the block selection signals of the remained group signals are preferentially allowed to be outputted.

Claim 5

Dependent Claim 107 words

A dynamic random access memory device (DRAM) according to any one of claims 1 to 3, characterized in that said memory block comprises said sub-array (MCA0..3; 10-13) of memory cells (MC) arranged in a matrix having a plurality of word lines (WLi) and a plurality of bit lines (BLi), and a plurality of sense amplifiers (SAi) each being attached to each of said bit lines (BLi) for amplifying output signals from said bit lines (BLi), a word decoder (WD0..3) and a column decoder (CD0..3), said word decoder (WD0..3) and said column decoder (CD0..3) are respectively used for selecting said word lines (WLi) and said bit lines (BLi).

Claim 6

Dependent Claim 97 words

A dynamic random access memory device (DRAM) according to claim 3 or 4, characterized in that said priority providing means comprises: a memory means for storing data of information regarding the precedent refresh operation or access operation; and a refresh/access selection means (46) having a memory means for storing a predetermined block selection schedule of said refresh operation and said access operation to be performed, such that said refresh block selection signals and said access block selection signals are selectively outputted according to said data stored in said memory means and said stored predetermined block selection schedule.

Claim 7

Dependent Claim 44 words

A dynamic random access memory device (DRAM) according to claim 2 or 4, characterized in that said double selection signal (EQ) from said comparison circuit (49) is outputted as a busy signal (BSY) to the associated outer circuit to stop the operation thereof temporarily.

Claim 8

Dependent Claim 46 words

A dynamic random access memory device (DRAM) by claim 3 or 4, characterized in that said double selection signal (EQ) from said priority providing means circuit (46, 48) is outputted as a busy signal (BSY) to the associated outer circuit to stop the operation thereof temporarily.

Claim 9

Dependent Claim 287 words

A dynamic random access memory device (DRAM) according to any one of claims 1-7, characterized in that each of said plurality of memory blocks includes one of said sub-arrays (MCAi) having a plurality of memory cells (MC) in a matrix, a plurality of word lines (WLi) and a plurality of bit lines (BLi), a plurality of sense amplifiers (SAi) each of which is attached to each of said bit line (BLi) and a column decoder (CDi) for said bit lines (BLi) of said sub-array and said device further comprising a pair of common word decoders (CWDL, CDWR), a first word decoder and a second word decoder and a plurality of word bus lines, each of said word bus line comprising: a pair of common word lines (CWLRi, CWLLi) disposed along each row of said memory cells (MC) of the said array comprising a first common word line connected to said first word decoder and a second common word line connected to said second common word decoder; a pair of a first block selection line and a second block selection line corresponding to each column of said array; and a pair (GLi, GRi) of a first switching means and a second switching means, each of said word lines located on said row of said array is selectively connected to said first common word line by activating each of corresponding first switching means through said first common word line and said first block selection line, and to said second common word line by activating each of corresponding second switching means through said second common word line and said second block selection line; thus said word line of said sub-array areselectively controllable by said two common word decorders (CWDL, CWDR).

Claim 10

Dependent Claim 24 words

A dynamic random access memory device (DRAM) according to claim 8, characterized in that said switching means is a field effect transistor (MOS FET).

Claim 11

Dependent Claim 61 words

A dynamic random access memory device (DRAM) according to claim 8 or 9, characterized in that said two common word decoders (CWDL, CWDR) are disposed on peripheral areas located at both sides of said array of memory cells (MCi) and said common word lines (WLi) are disposed in parallel with said row of said memory cells (MCi) on said semiconductor substrate.

Claim 12

Dependent Claim 172 words

A dynamic random access memory device (DRAM) according to any one of claims 8 to 10, characterized in that said common word bus line further comprises: N pairs of a first block selection line and a second block selection line corresponding to each column of said array, hereby N is an integer; and N pairs of a first switching means and a second switching means, each of said word lines (WLi) located on said row of said array is selectively connected to said first common word line by activating each of corresponding first switching means through said first common word line and said first block selection line, and to said second common word line by activating each of corresponding second switching means through said second common word line and said second block selection line, thus N+1 pieces of said word lines (WLi) of each of said sub-arrays (MCA0..3) are selectively controllable by said two common word decoders (CWDL, CWDR), thus enabling the number of said common lines to be reduced to 1/(N+1).

Claim 13

Dependent Claim 210 words

A random access memory device (RAM) formed on a semiconductor substrate characterized in that an array of memory cells (MCi) arranged in a matrix, said array being divided into a plurality of sub-arrays (MCAO..3) (subsections) of said memory cells (MC), each of said sub-arrays having a plurality of memory cells (MC) in a matrix, a plurality of word lines (WLi)and a plurality of bit lines (BLi), and a column decoder (CD0..3) for selecting said bit lines (BLi) a common word decoder (CWD); and a plurality of common word bus line (CWLi) for selecting said word lines located on a row of memory cells (MC) of said sub-array, each of said common bus line comprising: N pairs of block selection lines corresponding to each column of said array, hereby N is an integer; and N pairs of switching means, each of said word lines located on said row of said array is selectively connected to said common word line by activating each of corresponding switching means through said common word line and said block selection line, thus N pieces of said word lines of each of said sub- arrays are selectively controllable by said common word decoder, thus enabling the number of said common word lines to be reduced to 1/N.

Claim 14

Dependent Claim 210 words

A random access memory device (RAM) formed on a semiconductor substrate characterized in that an array of memory cells (MCi) arranged in a matrix, said array being divided into a plurality of sub-arrays (MCAO..3) (subsections) of said memory cells (MC), each of said sub-arrays having a plurality of memory cells (MC) in a matrix, a plurality of word lines (WLi)and a plurality of bit lines (BLi), and a column decoder (CD0..3) for selecting said bit lines (BLi) a common word decoder (CWD); and a plurality of common word bus line (CWLi) for selecting said word lines located on a row of memory cells (MC) of said sub-array, each of said common bus line comprising: N pairs of block selection lines corresponding to each column of said array, hereby N is an integer; and N pairs of switching means, each of said word lines located on said row of said array is selectively connected to said common word line by activating each of corresponding switching means through said common word line and said block selection line, thus N pieces of said word lines of each of said sub- arrays are selectively controllable by said common word decoder, thus enabling the number of said common word lines to be reduced to 1/N.

Random access memory device formed on a semiconductor substrate having an array of memory cells divided in sub-arrays

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