Carrier to noise ratio measurement circuit
Abstract
Abstract The circuit comprises a bandpass filter (301) for band-limiting an input signal; a first branching circuit (310) for branching the output of the bandpass filter (301) to produce two outputs; a first π/2 phase shifter (308) for rotating the phase of one of the two outputs of the first branching circuit by π/2 radians; an amplitude-limiter (302) for limiting the amplitude of the output of the first π/2 phase shifter (308); a second π/2 phase shifter (309) for rotating the phase of the output of the amplitude-limiter (302) by another π/2 radians; a second branching circuit (311) for branching the output of the second π/2 phase shifter to produce two outputs; a delay circuit (303) for delaying one of the two outputs of the second branching circuit (311); a third branching circuit (312) for branching the output of the delay circuit to produce two outputs; a first multiplier (305) for producing a product of one of the two outputs of the third branching circuit (312) and the other output of the first branching circuit (310); a third n/2 phase shifter (306) for rotating the phase of the other output of the third branching circuit (306) by ir/2 radians; a second multiplier (304) for producing a product of the output of the third π/2 phase shifter (306) and the other output of the second branching circuit (311) and a logical processor (307). This processor averages and squares the output of the multiplier (305) and divides the resultant signal by a signal produced by squaring and averaging the output of the multiplier (304).
Inventors
- 👤 Susumu Otani
Bibliographic Details
Claims Analysis
Total Claims: 3References Cited (Backward Citations)
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