EP0181177A2
Expired / Lapsed
EP
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A semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1985-11-04
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Granted: —
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Expires: 2005-11-04
Abstract
Abstract A semiconductor memory device operatively connected to a power source (V cc ,V ss ) includes a reference potential line (ℓ 2 ) operatively connected to receive a reference potential (V ss ) from the power source; an input circuit (21,Q 1 ,Q 2 ) which is connected to the reference potential line (ℓ 2 ) and receives an external input signal (WE) having a logic level defined with respect to the reference potential to be supplied to the reference potential line, an output circuit (22) having an external output terminal which may be connected to the reference potential line (f 2 ), for generating an output to the external output terminal, and an inhibiting circuit (Q 3 ) for inhibiting a response to the external input signal of the input circuit for a predetermined period during which the output of the output circuit changes.
Inventors
- 👤 Shigeki Nozaki
- 👤 Tsuyoshi Ohira
- 👤 Masaru Satoh
- 👤 Tomio Nakano
- 👤 Yoshihiro Takemae
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 02:53
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C7/00; G11C7/22; G11C8/00; G11C8/18
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
113 words
A semiconductor memory device operatively connectable to a power source including: a reference potential line operatively connected to receive a reference potential from said power source; an input circuit connected to said reference potential line and receiving an external input signal having a logic level defined in reference to said reference potential to be supplied to said source potential line; an output circuit having an external output terminal, connected to said reference potential line, for generating an output to said external output terminal; and an inhibiting circuit for inhibiting a response to said external input signal of said input circuit for a predetermined period during which the output of said output circuit changes.
Claim 2
Dependent Claim
113 words
A semiconductor memory device operatively connectable to a power source including: a reference potential line operatively connected to receive a reference potential from said power source; an input circuit connected to said reference potential line and receiving an external input signal having a logic level defined in reference to said reference potential to be supplied to said source potential line; an output circuit having an external output terminal, connected to said reference potential line, for generating an output to said external output terminal; and an inhibiting circuit for inhibiting a response to said external input signal of said input circuit for a predetermined period during which the output of said output circuit changes.
Claim 3
Dependent Claim
106 words
A semiconductor memory device according to Claim 1, wherein said input circuit provides a MOS transistor which receives a write enable bar signal having a TTL level and outputs an inverted signal of said write enable bar signal having a MOS level, said output circuit provides an output stage transistor connected to the reference potential line and outputs a low level output by turning said output stage transistor ON, and said inhibiting circuit is formed by a transistor which is connected in parallel with said MOS transistor in said input circuit and which turns ON for a predetermined period during which said output transistor turns ON.
Claim 4
Dependent Claim
128 words
A semiconductor memory device operatively connectable to a power source including: a reference potential line operatively connected to receive a reference potential from said power source; an input circuit connected to said reference potential line and receiving an external input signal having a logic level defined in reference to said reference potential to be supplied to said source potential line; an output circuit having an external output terminal, connected to said reference potential line, for generating an output to said external output terminal; and a switching circuit under control of a switching control signal derived using a clock signal of the device, for enabling a correct response of said input circuit to said external input signal, even under a condition of a temporary change in the reference potential.
Claim 5
Dependent Claim
128 words
A semiconductor memory device operatively connectable to a power source including: a reference potential line operatively connected to receive a reference potential from said power source; an input circuit connected to said reference potential line and receiving an external input signal having a logic level defined in reference to said reference potential to be supplied to said source potential line; an output circuit having an external output terminal, connected to said reference potential line, for generating an output to said external output terminal; and a switching circuit under control of a switching control signal derived using a clock signal of the device, for enabling a correct response of said input circuit to said external input signal, even under a condition of a temporary change in the reference potential.
Claim 6
Dependent Claim
21 words
A semiconductor memory device as claimed in claim 3, wherein said switching control signal is the same as the clock signal.
Claim 7
Dependent Claim
40 words
A semiconductor memory device as claimed in claim 3, wherein said switching control signal is a pulse signal of a duration longer than said temporary change in the reference potential but shorter than a clock pulse of said clock signal.
Claim 8
Dependent Claim
24 words
A semiconductor memory device as claimed in claim 3, 4 or 5, wherein said external input signal is a write enable bar (WE) signal.
Claim 9
Dependent Claim
33 words
A semiconductor memory device as claimed in any one of claims 3 to 6, wherein said reference potential is a MOS level potential and said external input signal is a TTL level signal.
Claim 10
Dependent Claim
22 words
A semiconductor memory device as claimed in claim 7, wherein said reference potential is a low MOS level potential (V SS ).
Claim 11
Dependent Claim
34 words
A semiconductor memory device as claimed in any of claims 3 to 8, wherein said switching circuit comprises a MOS transistor, connected in parallel with a MOS transistor which receives said external input signal.
References Cited (Backward Citations)
No citation records indexed.
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