EP0181162A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A single transistor/capacitor semiconductor memory device and method for manufacture
Assignee: Toshiba Corp
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Filing: 1985-10-31
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Granted: —
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Expires: 2005-10-31
Abstract
Abstract A method of manufacturing a semiconductor memory device provides increased capacitance from memory cells of a dynamic RAM. In this method there are formed a plurality of island regions surrounded by an insulating layer (6) embedded in field regions (4) of a semiconductor substrate (t) so that the insulating layer (6) has a flat surface in the field regions (4). An etching mask (7) is formed on the substrate (1) and continues across a middle part of each of the island regions in a first direction. The insulating layer (6) is etched where it is not covered by the etching mask (7). Capacitor electrodes (8,10) are formed so as to be separated by a thin insulating film (9) and cover the exposed lateral walls and upper surfaces of the island regions. Then gate insulating films (11) are formed on the upper surface of the middle part of the island regions after removing the etching mask (7). A gate electrode (12) is formed for each transistor, the gate electrodes (12) continuing across the plurality of island regions in the first direction. The gate electrodes (12) are so disposed as to constitute word lines while bit lines (16) connect the drains of the MOS transistors in the memory cells.
Inventors
- 👤 Masashi C/O Patent Division Toshiba Wada
- 👤 Shigeyoshi C/O Patent Division Toshiba Watanabe
- 👤 Fujio C/O Patent Division Toshiba Masuoka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 10:26
CPC Classifications
H; H10; H10B; H10B12/00; H10B12/01; H10B12/02; H10B12/03; H10B12/038; H10B12/30; H10B12/37; H10D; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D1/665; H10W; H10W10/00; H10W10/01; H10W10/011; H10W10/012; H10W10/0121; H10W10/014; H10W10/10; H10W10/13; H10W10/17
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
176 words
A method of manufacturing a semiconductor memory device comprising memory cells each having one capacitor and one transistor, said method comprising the steps of: (a) forming a plurality of island regions surrounded by an insulating layer (6) embedded in field regions (4) of a semiconductor substrate (1) such that said insulating layer (6) has a flat surface in said field regions (4); (b) forming an etching mask (7) on said substrate (1) continuing across a middle part of each of said island regions in a first direction; (c) etching said insulating layer (6) not covered by said etching mask (7); (d) forming capacitor electrodes (8, 10) separated by a thin insulating film (9) and covering the exposed lateral walls and upper surfaces of said island regions; (e) forming gate insulating films (11) on the upper surfaces of said middle part of said island regions after removing said etching mask (7); and (f) forming a gate electrode (12) for each said transistor, said gate electrode (12) continuing across said plurality of island regions in said first direction.
Claim 2
Independent Claim
176 words
A method of manufacturing a semiconductor memory device comprising memory cells each having one capacitor and one transistor, said method comprising the steps of: (a) forming a plurality of island regions surrounded by an insulating layer (6) embedded in field regions (4) of a semiconductor substrate (1) such that said insulating layer (6) has a flat surface in said field regions (4); (b) forming an etching mask (7) on said substrate (1) continuing across a middle part of each of said island regions in a first direction; (c) etching said insulating layer (6) not covered by said etching mask (7); (d) forming capacitor electrodes (8, 10) separated by a thin insulating film (9) and covering the exposed lateral walls and upper surfaces of said island regions; (e) forming gate insulating films (11) on the upper surfaces of said middle part of said island regions after removing said etching mask (7); and (f) forming a gate electrode (12) for each said transistor, said gate electrode (12) continuing across said plurality of island regions in said first direction.
Claim 3
Dependent Claim
31 words
A method according to claim 1 further comprises the steps of: using different types of impurities for doping said island regions; and using said etching mask (7) as a doping mask.
Claim 4
Dependent Claim
57 words
A method according to claim 1 or 2 wherein said island regions forming step comprises the steps of: forming grooves (4) by the reactive ion etching method; covering said insulating layer (6) with photo-resist (7) for smoothing the surface of said substrate; and etching said insulating layer (6) and said photo-resist (7) at substantially equal etching speeds.
Claim 5
Dependent Claim
44 words
A method of claim 1 wherein said island regions forming step comprises the steps of: forming said insulating layer (6) on said substrate; and growing a semiconductor layer on the exposed surface of said substrate to substantially the same thickness as said insulating layer.
Claim 6
Dependent Claim
93 words
A method according to claim 1 or 2 wherein said capacitor electrode forming step includes the step of forming said capacitor electrode (10) of a first layer of polycrystalline silicon film: wherein said step of forming said gate electrode includes the step of forming said gate electrode (12) of a second layer of polycrystalline silicon film; and wherein said method further includes the step of using said first and second layers of polycrystalline silicon films (10, 12) as doping masks for forming the source and drain regions (13, 14) of said MOS transistor.
Claim 7
Dependent Claim
26 words
A method according to claim 1 wherein said island regions forming step includes the step of using each of said island regions for two memory cells.
Claim 8
Dependent Claim
29 words
A method according to claim 1 wherein said etching step comprises the step of etching away said insulating layer (6), except for a prescribed thickness necessary for device isolation.
Claim 9
Independent Claim
22 words
A method according to claim I further including the step of doping impurities, same type of conductivity under said insulating layer (6).
Claim 10
Dependent Claim
194 words
A semiconductor memory comprising: (a) a plurality of memory cells formed on a substrate of a first conductivity type, each said memory cell including: (i) an MOS transistor having a gate (12) and a conduction path, and (ii) an MOS capacitor coupled to one side of said conduction path, said MOS capacitor including (aa) a first electrode (8) of a second conductivity type formed in said substrate (1) in contact with said one side of said conduction path, said first electrode (8) having at least three sides; (bb) a thin insulation film (9) formed on said first electrode to cover said three sides of said first electrode (8); (cc) a second electrode (10) formed on said thin insulation film (9) and opposite each of said at least three faces, and (dd) a device protection film (15) formed on said second electrode (10); (b) a plurality of word lines each coupled to the gates (12) of ones of said plurality of MOS transistors in a different row; and (c) a plurality of bit lines (16) each coupled to the other side of the conduction paths of ones of said MOS transistors in a different column.
Claim 11
Dependent Claim
194 words
A semiconductor memory comprising: (a) a plurality of memory cells formed on a substrate of a first conductivity type, each said memory cell including: (i) an MOS transistor having a gate (12) and a conduction path, and (ii) an MOS capacitor coupled to one side of said conduction path, said MOS capacitor including (aa) a first electrode (8) of a second conductivity type formed in said substrate (1) in contact with said one side of said conduction path, said first electrode (8) having at least three sides; (bb) a thin insulation film (9) formed on said first electrode to cover said three sides of said first electrode (8); (cc) a second electrode (10) formed on said thin insulation film (9) and opposite each of said at least three faces, and (dd) a device protection film (15) formed on said second electrode (10); (b) a plurality of word lines each coupled to the gates (12) of ones of said plurality of MOS transistors in a different row; and (c) a plurality of bit lines (16) each coupled to the other side of the conduction paths of ones of said MOS transistors in a different column.
Claim 12
Dependent Claim
55 words
A semiconductor memory according to claim 9 wherein said memory cells are formed on island regions of said substrate, each island region having a top and at least two sides and wherein said at least three sides of said electrode (8) include portions of the top and at least two sides of said island regions.
Claim 13
Dependent Claim
17 words
A semiconductor memory according to claim 10 wherein two memory cells are formed on each island region.
Claim 14
Dependent Claim
66 words
A semiconductor memory according to claim 10 wherein said island regions are separated by grooves (4) and wherein said memory further comprises a device separation region (5) of said first conductivity type at the bottom of each said groove (4) and a field isolation film ( 6 ) filling part of said groove, said field isolation film (6) having a top surface which is substantially flat.
Claim 15
Dependent Claim
41 words
1 3 . A semiconductor memory according to claim 9 wherein said thin insulation film (9) includes a thermal oxide film, wherein said device protection film (15) comprises Si0 2 , and wherein said word lines (16) comprise polycrystalline silicon film.
References Cited (Backward Citations)
No citation records indexed.
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