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EP0180725A2
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Instruction prefetch operation for branch instructions
Assignee: International Business Machines Corp
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Filing: 1985-08-20
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Granted: —
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Expires: 2005-08-20
Abstract
Abstract @ A method is described for expanding the capability of an instruction prefetch buffer (11). The method enables the instruction prefetch buffer to distinguish between old prefetches that occurred before a branch in an instruction stream and new prefetches which occurred after the branch in the instruction stream. A control tag is generated each time a request for an instruction is sent to a storage. The returning instruction has appended thereto the original control tag which is then compared to the current value of control tag in the instruction prefetch buffer. If the two values match, then this is an indication that a branch has not occurred and the instruction is still required. However, if the two values of the control tag are not equal, then this is an indication that a branch in the instruction stream has occurred and that the instruction being sent from storage to the buffer is no longer required. The method is are also applicable to the use of branch-with-execute instructions wherein a subject instruction is executed immediately following the branch-with-execute instruction. The execution of this subject instruction before the branch target instruction enables the system processor to continue operating while it is waiting for the branch target instruction.
Inventors
- 👤 Philippe Doyce Hester
- 👤 William Michael Johnson
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 03:26
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804; G06F9/3836; G06F9/3842; G06F9/3885; G06F9/3889
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
105 words
In a processing system including a processor and a storage from which said processor prefetches instructions, a method for executing a plurality of instructions having at least one branch instruction, said method being characterized in that it comprises: generating a control tag whose current value is changed each time a branch instruction is reached; sending a request for instructions to said storage; appending said control tag to each request sent to said storage; and, retaining each returned instruction from said storage until execution, subsequent to the value of control tag accompanying each said returned instruction being equal to the current value of the control tag.
Claim 2
Dependent Claim
105 words
In a processing system including a processor and a storage from which said processor prefetches instructions, a method for executing a plurality of instructions having at least one branch instruction, said method being characterized in that it comprises: generating a control tag whose current value is changed each time a branch instruction is reached; sending a request for instructions to said storage; appending said control tag to each request sent to said storage; and, retaining each returned instruction from said storage until execution, subsequent to the value of control tag accompanying each said returned instruction being equal to the current value of the control tag.
Claim 3
Dependent Claim
31 words
A method according to Claim 1 further comprising the step of appending a number to each request for instruction identifying a location to which each returned instruction is to be sent.
Claim 4
Dependent Claim
27 words
A method according to Claim 1 or 2 further.comprising the step of setting a control signal each time a request for instruction is sent to said storage.
Claim 5
Dependent Claim
45 words
A method according to Claim 9 further comprising the step of resetting said control signal subsequent to the value of control tag accompanying each returned instruction being unequal to the current value of said control tag, thereby indicating that a branch instruction has been reached.
Claim 6
Dependent Claim
77 words
In a processing system including a processor and a storage from which said processor prefetches instructions, a method for executing a plurality of instructions having at least one branch-with-execute instruction, said method being characterized in that it includes : fetching a branch-with-execute instruction from said storage; fetching a subject instruction from said storage while simultaneously executing said branch-with-execute instruction; fetching a target instruction from said storage while simultaneously executing said subject instruction; and, executing said target instruction.
Claim 7
Dependent Claim
77 words
In a processing system including a processor and a storage from which said processor prefetches instructions, a method for executing a plurality of instructions having at least one branch-with-execute instruction, said method being characterized in that it includes : fetching a branch-with-execute instruction from said storage; fetching a subject instruction from said storage while simultaneously executing said branch-with-execute instruction; fetching a target instruction from said storage while simultaneously executing said subject instruction; and, executing said target instruction.
Claim 8
Dependent Claim
71 words
In a processing system including a processor and a storage from which said processor prefetches instructions, a method for executing a plurality of instructions having at least one branch-with-execute instruction, said method being characterized in that it comprises: executing said branch-with-execute instruction; determining a location in an instruction buffer for holding a target instruction prior to execution; and, freeing all locations in said instruction buffer not associated with a subject instruction.
Claim 9
Dependent Claim
71 words
In a processing system including a processor and a storage from which said processor prefetches instructions, a method for executing a plurality of instructions having at least one branch-with-execute instruction, said method being characterized in that it comprises: executing said branch-with-execute instruction; determining a location in an instruction buffer for holding a target instruction prior to execution; and, freeing all locations in said instruction buffer not associated with a subject instruction.
Claim 10
Dependent Claim
41 words
A method according to Claim 6 further comprising: executing said subject instruction; freeing the location in said instruction buffer in which said subject instruction was held prior to execution; and, fetching said target instruction from said storage to said instruction buffer.
Claim 11
Dependent Claim
34 words
A method according to Claim 7 further comprising the step of updating a pointer in said instruction buffer prior to fetching said target instruction, said updating step enabling the decoding of said target instruction.
Claim 12
Dependent Claim
29 words
A method according to Claim 8 further comprising the step of allocating a location in said instruction buffer associated with the value of said pointer for said target instruction.
Claim 13
Dependent Claim
19 words
A method according to Claim 9 further comprising decoding said target instruction at said location in said instruction buffer.
References Cited (Backward Citations)
No citation records indexed.
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