Microprogramme sequence controller

Claim 2

A microprogram sequence controller which cyclically processes instructions and generates instruction addresses on a bidirectional output data bus, said controller capable of being selectively operated in an interrupt mode or a trapped mode, including instruction decoding means for generating a plurality of control signals, and last-in, first-out memory means connected to said instruction decoding means and responsive to said control signals for receiving and storing a plurality of instruction addresses, said microprogram sequence controller responsive to interrupt-mode signals and to trap-mode signals and further including instruction address counter means responsive to said interrupt-and trap-mode signals for receiving an instruction address, for selectively incrementing, for storing said address, and for generating said instruction address at an output, and interrupt/trap logic means connected to said instruction decoding means and to said instruction address counter means for receiving said interrupt-mode and trap-mode signals, for generating when said controller is in said interrupt-mode gating signals that cause incrementation of said instruction address received by said address counter means, that inhibit communication of said instruction address on said bidirectional output data bus ("interrupt return address"), that cause said instruction decoding means to generate control signals which cause to be stored said interrupt return address in said last-in, first-out memory means, that cause to be received on said bidirectional data output bus the address of the first instruction of an interrupt subroutine ("interrupt address") and that cause to be stored said interrupt address in said address counter means, and for generating when said controller is in said trap-mode gating signals that inhibit incrementation of said instruction address received by said address counter means, that inhibit communication of said instruction address ("trap return address") on said bidirectional output data bus, that cause said instruction decoding means to generate control signals that cause to be stored said trap return address in said last-in, first-out memory means, that cause to be received on said bidirectional data output bus the address of the first instruction of a trap subroutine ("trap address") and that cause to be stored said trap address in said address counter means.

Claim 3

The interruptible and trappable microprogram sequence controller of claim 1 wherein said controller is responsive to a clock signal further including: (a) first multiplexer means connected to said last-in, first-out memory means, to said address counter means and to said instruction decoding means, responsive to said control signals generated by said decoding means for selectively coupling said last-in, first-out memory means or said address counter means to an output of said first multiplexer means, said output being said currently-generated instruction address, (b) return address latch means connected between said output of said first multiplexer means and said last-in, first-out memory means responsive to said clock signal for receiving an instruction address and temporarily storing said address during a clock cycle and for transmitting during the next-following clock cycle said instruction address to said last-in, first-out memory means, (c) tri-state driver means connected to said interrupt/trap logic means, receiving at an input the output of said first multiplexer means, and connected at an output to said bidirectional output bus, responsive to said gating signals generated by said interrupt/trap means, for selectively coupling or inhibiting said communication of said currently-generated instruction address onto said bidirectional output data bus, and (d) second multiplexer means connected to said output of said tri-state driver means, to said output of said first multiplexer means, to said address counter means, and to said interrupt/trap logic means, responsive to said gating signals generated by said interrupt/trap means, for selectively coupling said output of said first multiplexer means or said bidirectional output data bus to said address counter means; whereby, during a clock cycle when said controller is in said interrupt mode, said interrupt/trap logic means causes said tri-state driver means to inhibit communication of said interrupt return address from said first multiplexer means output to said bidirectional output data bus, causes said interrupt return address to be communicated from said address counter means via said first multiplexer means, and at the next following clock cycle via said return address latch means to said last-in, first-out memory means, and causes said interrupt address to be communicated via said bidirectional data output bus and said second multiplexer means to said address counter means, and whereby, during a clock cycle when said controller is in said trap mode, said interrupt/trap logic means causes said tri-state driver means to inhibit communication of said trap return address from said first multiplexer means output to said bidirectional data output bus, causes said trap return address to be communicated from said address counter means via said first multiplexer means, and at the next-following clock cycle, via said return address latch means to said last-in, first-out memory means, and causes said trap address to be communicated via said bidirectional data output bus and said second multiplexer means to said address counter means.

Claim 4

The interruptible and trappable microprogram sequence controller of claim 2 wherein said trap-mode signals include a carry-in to incrementer signal and said address counter means comprises: address latch means connected to said output of said second multiplexer means responsive to said clock signal for receiving and temporarily storing for one clock cycle said instruction address received by said address counter means, and incrementer means connected to said address latch means, and to said interrupt/trap logic means, and having an output connected to said first multiplexer means, responsive to said interrupt/trap gating signals and to said carry-in signal for receiving during said next-following clock cycle said instruction address temporarily stored in said address latch means, for selectively incrementing said address in response to said gating and carry-in signals, and for generating said resulting address on said output connected to said first multiplexer means, whereby, during said interrupt-mode said instruction address generated on said bidirectional output data bus received and temporarily stored by said address latch means, is incremented by said incrementer means, and whereby, during said trap-mode said instruction address generated on said bidirectional output data bus received and temporarily stored by said address latch means, is not incremented by said incrementer means.

Claim 5

A microprogram sequence controller which cyclically processes instructions and generates instruction addresses on a bidirectional output data bus, said controller capable of being selectively operated in an interrupt mode or a trapped mode, including instruction decoding means for generating a plurality of control signals, and last-in, first-out memory means connected to said instruction decoding means and responsive to said control signals for receiving and storing a plurality of instruction addresses, said microprogram sequence controller responsive to interrupt-mode signals and to trap-mode signals and to a clock signal and further including: (a) instruction address counter means responsive to said interrupt- and trap-mode signals for receiving an instruction address, for selectively incrementing, for storing said address, and for generating said instruction address at an output, (b) first multiplexer means connected to said last-in, first-out memory means, to said address counter means and to said instruction decoding means, responsive to said control signals generated by said decoding means for selectively coupling said last-in, first-out memory means or said address counter means to an output of said first multiplexer means, said output being the "currently-generated instruction address," (c) interrupt/trap logic means connected to said instruction decoding means and to said instruction address counter means for receiving said interrupt-mode and said trap-mode signals, for generating when said controller is in said interrupt mode gating signals that cause incrementation of said instruction address received by said address counter means, that inhibit communication of said currently-generated instruction address on said bidirectional output data by ("interrupt return address"), that cause said instruction decoding means to generate control signals which cause to be stored said interrupt return address in said last-in, first-out memory means, that cause to be received on said bidirectional data output bus the address of the first instruction of an interrupt subroutine ("interrupt address"), and that cause to be stored said interrupt address in said address counter means, and for generating when said controller is in said trap mode gating signals that inhibit incrementation of said instruction address received by said address counter means, that inhibit communication of said currently-generated instruction address on said bidirectional output data bus ("trap return address"), that cause said instruction decoding means to generate control signals that cause to be stored said trap return address in said last-in, first-out memory means, that cause to be received on said bidirectional data output bus the address of the first instruction of a trap subroutine ("trap address"), and that cause to be stored said trap address in said address counter means, (d) tri-state driver means connected to said interrupt/trap logic means, receiving at an input the output of said first multiplexer means, and connected at an output to said bidirectional output data bus, responsive to said gating signals generated by said interrupt/trap means, for selectively coupling or inhibiting said communication of said currently-generated instruction address onto said bidirectional output data bus, (e) second multiplexer means connected to said output of said tri-state driver means, to said output of said first multiplexer means, to said address counter means, and to said interrupt/trap logic means, responsive to said gating signals generated by said interrupt/trap means, for selectively coupling said output of said first multiplexer means or said bidirectional output data bus to said address counter means, and (f) return address latch means connected between said first multiplexer means and said last-in, first-out memory means responsive to said clock signal for receiving an instruction address and temporarily storing said address during a clock cycle and for transmitting during the next-following clock cycle said instruction address to said last-in, first-out memory means, whereby, during a clock cycle when said controller is in said interrupt mode, said interrupt/trap logic means causes said tri-state driver means to inhibit communication of said interrupt return address from said first multiplexer means output to said bidirectional output data bus, causes said interrupt return address to be communicated from said first multiplexer means, and causes said interrupt address to be communicated via said bidirectional data output bus and said second multiplexer means to said address counter means, and at the next following clock cycle via said return address latch means to said last-in, first-out memory means, and whereby, during a clock cycle when said controller is in said trap mode, said interrupt/trap logic means causes said tri-state driver means to inhibit communication of said trap return address from said first multiplexer means output to said bidirectional data output bus, causes said trap return address to be communicated from said address counter means via said first multiplexer means, and causes said trap address to be communicated via said bidirectional data output bus and said second multiplexer means to said address counter means, and at the next-following clock cycle, via said return address latch means to said last-in, first-out memory means,

Claim 6

A microprogram sequence controller which cyclically processes instructions and generates instruction addresses on a bidirectional output data bus, said controller capable of being selectively operated in an interrupt mode or a trapped mode, including instruction decoding means for generating a plurality of control signals, and last-in, first-out memory means connected to said instruction decoding means and responsive to said control signals for receiving and storing a plurality of instruction addresses, said microprogram sequence controller responsive to interrupt-mode signals and to trap-mode signals and to a clock signal and further including: (a) instruction address counter means responsive to said interrupt- and trap-mode signals for receiving an instruction address, for selectively incrementing, for storing said address, and for generating said instruction address at an output, (b) first multiplexer means connected to said last-in, first-out memory means, to said address counter means and to said instruction decoding means, responsive to said control signals generated by said decoding means for selectively coupling said last-in, first-out memory means or said address counter means to an output of said first multiplexer means, said output being the "currently-generated instruction address," (c) interrupt/trap logic means connected to said instruction decoding means and to said instruction address counter means for receiving said interrupt-mode and said trap-mode signals, for generating when said controller is in said interrupt mode gating signals that cause incrementation of said instruction address received by said address counter means, that inhibit communication of said currently-generated instruction address on said bidirectional output data by ("interrupt return address"), that cause said instruction decoding means to generate control signals which cause to be stored said interrupt return address in said last-in, first-out memory means, that cause to be received on said bidirectional data output bus the address of the first instruction of an interrupt subroutine ("interrupt address"), and that cause to be stored said interrupt address in said address counter means, and for generating when said controller is in said trap mode gating signals that inhibit incrementation of said instruction address received by said address counter means, that inhibit communication of said currently-generated instruction address on said bidirectional output data bus ("trap return address"), that cause said instruction decoding means to generate control signals that cause to be stored said trap return address in said last-in, first-out memory means, that cause to be received on said bidirectional data output bus the address of the first instruction of a trap subroutine ("trap address"), and that cause to be stored said trap address in said address counter means, (d) tri-state driver means connected to said interrupt/trap logic means, receiving at an input the output of said first multiplexer means, and connected at an output to said bidirectional output data bus, responsive to said gating signals generated by said interrupt/trap means, for selectively coupling or inhibiting said communication of said currently-generated instruction address onto said bidirectional output data bus, (e) second multiplexer means connected to said output of said tri-state driver means, to said output of said first multiplexer means, to said address counter means, and to said interrupt/trap logic means, responsive to said gating signals generated by said interrupt/trap means, for selectively coupling said output of said first multiplexer means or said bidirectional output data bus to said address counter means, and (f) return address latch means connected between said first multiplexer means and said last-in, first-out memory means responsive to said clock signal for receiving an instruction address and temporarily storing said address during a clock cycle and for transmitting during the next-following clock cycle said instruction address to said last-in, first-out memory means, whereby, during a clock cycle when said controller is in said interrupt mode, said interrupt/trap logic means causes said tri-state driver means to inhibit communication of said interrupt return address from said first multiplexer means output to said bidirectional output data bus, causes said interrupt return address to be communicated from said first multiplexer means, and causes said interrupt address to be communicated via said bidirectional data output bus and said second multiplexer means to said address counter means, and at the next following clock cycle via said return address latch means to said last-in, first-out memory means, and whereby, during a clock cycle when said controller is in said trap mode, said interrupt/trap logic means causes said tri-state driver means to inhibit communication of said trap return address from said first multiplexer means output to said bidirectional data output bus, causes said trap return address to be communicated from said address counter means via said first multiplexer means, and causes said trap address to be communicated via said bidirectional data output bus and said second multiplexer means to said address counter means, and at the next-following clock cycle, via said return address latch means to said last-in, first-out memory means,

Claim 7

The interruptible and trappable microprogram sequence controller of claim 4 wherein said trap-mode signals include a carry-in to incrementer signal and said instruction address counter means comprises: address latch means connected to said output of said second multiplexer means responsive to said clock signal for receiving and temporarily storing for one clock cycle said instruction address received by said address counter means, and incrementer means connected to said address latch means, and to said interrupt/trap logic means, and having an output connected to said first multiplexer means responsive to said interrupt/trap gating signals and to said carry-in signal for receiving during said next-following clock cycle said instruction address temporarily stored in said address latch means, for selectively incrementing said address in response to said gating and carry-in signals, and for generating said resulting address on said output connected to said first multiplexer means, whereby, during said interrupt-mode said currently-generated instruction address received and temporarily stored by said address latch means, is incremented by said incrementer means, and whereby, during said trap-mode said instruction address generated on said bidirectional output data bus received and temporarily stored by said address latch means, is not incremented by said incrementer means.

Claim 8

In a microprogram sequence controller which cyclically processes instructions and generates instruction addresses on a bidirectional output data bus, including instruction decoding means for generating a plurality of control signals, and last-in, first-out memory means connected to said instruction decoding means and responsive to said control signals for receiving and storing a plurality of instruction addresses, said microprogram sequence controller responsive to interrupt-mode signals and to trap-mode signals and further including instruction address counter means responsive to said interrupt- and trap-mode signals for receiving an instruction address, for selectively incrementing, for storing said address, and for generating said instruction address at an output and interrupt/trap logic means connected to said instruction decoding means and to said instruction address counter means for receiving said interrupt-mode, said trap-mode signals and an instruction address, the method of selectively operating said microprogram sequence controller in an interrupt mode or a trap-mode comprising upon receipt by said interrupt/trap means of said interrupt-mode signal, the steps; (a) incrementing said instruction address received by said address counter means, (b) inhibiting communication of said instruction address on said bidirectional output data bus ("interrupt return address"), (c) storing said interrupt return address in said last-in, first-out memory means, (d) receiving on said bidirectional output data bus the address of the first instruction of an interrupt subroutine ("interrupt address"), and (e) storing said interrupt address in said address counter means, upon receipt by said interrupt/trap means of said trap-mode signal, the steps; (f) inhibiting incrementation of said instruction address by said address counter means, (g) inhibiting communication of the instruction address on said bidirectional output data bus ("trap return address"), (h) storing said trap return address in said last-in, first-out memory means, (i) receiving on said bidirectional output data bus the address of the first instruction of a trap subroutine ("trap address"), and (j) storing said trap address in said address counter means.

Claim 9

In a microprogram sequence controller which cyclically processes instructions and generates instruction addresses on a bidirectional output data bus, including instruction decoding means for generating a plurality of control signals, and last-in, first-out memory means connected to said instruction decoding means and responsive to said control signals for receiving and storing a plurality of instruction addresses, said microprogram sequence controller responsive to interrupt-mode signals and to trap-mode signals and further including instruction address counter means responsive to said interrupt- and trap-mode signals for receiving an instruction address, for selectively incrementing, for storing said address, and for generating said instruction address at an output and interrupt/trap logic means connected to said instruction decoding means and to said instruction address counter means for receiving said interrupt-mode, said trap-mode signals and an instruction address, the method of selectively operating said microprogram sequence controller in an interrupt mode or a trap-mode comprising upon receipt by said interrupt/trap means of said interrupt-mode signal, the steps; (a) incrementing said instruction address received by said address counter means, (b) inhibiting communication of said instruction address on said bidirectional output data bus ("interrupt return address"), (c) storing said interrupt return address in said last-in, first-out memory means, (d) receiving on said bidirectional output data bus the address of the first instruction of an interrupt subroutine ("interrupt address"), and (e) storing said interrupt address in said address counter means, upon receipt by said interrupt/trap means of said trap-mode signal, the steps; (f) inhibiting incrementation of said instruction address by said address counter means, (g) inhibiting communication of the instruction address on said bidirectional output data bus ("trap return address"), (h) storing said trap return address in said last-in, first-out memory means, (i) receiving on said bidirectional output data bus the address of the first instruction of a trap subroutine ("trap address"), and (j) storing said trap address in said address counter means.