EP0180196A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Programmable counter/timer device
Assignee: Hitachi Ltd
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Filing: 1985-10-29
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Granted: —
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Expires: 2005-10-29
Abstract
Abstract A counter/timer device includes a plurality of registers (105) each capable of performing any of the function of a counter/timer register, the function of a capture register and the function of a compare register, in accordance with a command from a central processing unit, and a plurality of task registers (103) corresponding to tasks which are to be carried out by using the above registers. Each of the task registers stores a task instruction for specifying a counter/timer register and a capture/compare register which are used in a task, and for specifying the operation mode of each of the specified registers. The task registers are scanned to successively read out the task instructions, and each of the read-out task instructions controls the operation of each of registers used in a corresponding task. Thus, tasks corresponding to the task instructions are all carried out at once.
Inventors
- 👤 Shigeki Morinaga
- 👤 Mitsuru Watabe
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 08:46
CPC Classifications
G; G06; G06F; G06F7/00; G04; G04G; G04G99/00; G04G99/006; G04G15/00; G04G15/006; G06F9/00; G06F9/06; G06F9/22
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
180 words
A counter/timer device comprising: task instruction generating means (205) capable of successively generating a plurality of task instructions corresponding to counter/timer operations to be carried out, one by one; counter/timer operation means (207) including a register group (105) made up of a plurality of registers each capable of performing any of plural register functions necessary for said counter/timer operations, arithmetic unit means (106 to 109) for performing an arithmetic/logic operation on the basis of data from said register group, and bus means (116 to 118) for transferring data between said register group and said arithmetic unit means; and task instruction control means (206) connected between said task instruction generating means (205) and said counter/timer operation means (207), and in response to a task instruction generated by said task instruction generating means to specify at least one register which is included in said register group of said counter/timer operation means and corresponds to said task instruction, for causing said arithmetic unit means to perform an arithmetic/logic operation corresponding to said task instruction on the basis of data in the specified register.
Claim 2
Dependent Claim
180 words
A counter/timer device comprising: task instruction generating means (205) capable of successively generating a plurality of task instructions corresponding to counter/timer operations to be carried out, one by one; counter/timer operation means (207) including a register group (105) made up of a plurality of registers each capable of performing any of plural register functions necessary for said counter/timer operations, arithmetic unit means (106 to 109) for performing an arithmetic/logic operation on the basis of data from said register group, and bus means (116 to 118) for transferring data between said register group and said arithmetic unit means; and task instruction control means (206) connected between said task instruction generating means (205) and said counter/timer operation means (207), and in response to a task instruction generated by said task instruction generating means to specify at least one register which is included in said register group of said counter/timer operation means and corresponds to said task instruction, for causing said arithmetic unit means to perform an arithmetic/logic operation corresponding to said task instruction on the basis of data in the specified register.
Claim 3
Dependent Claim
104 words
A counter/timer device according to Claim 1, wherein said task instruction generating means (205) includes storage means (103) for storing each of a plurality of task instructions to be executed, at an address assigned thereto, task signal generating means (101) for generating a task signal capable of successively specifying task instructions stored in said storage means (103), and task address decoding means (102) connected between said storage means (103) and said task signal generating means (101) for decoding said task signal to give said storage means an address indicated by said task signal, thereby reading out a task instruction corresponding to said task signal.
Claim 4
Dependent Claim
18 words
A counter/timer device according to Claim 2, wherein said task signal generating means (101) includes a counter circuit.
Claim 5
Dependent Claim
36 words
A counter/timer device according to Claim 2, wherein said storage means (103) is a memory, for which a microcomputer unit (100) connected to the counter/timer device can perform both a writing operation and a reading operation.
Claim 6
Dependent Claim
29 words
A counter/timer device according to Claim 2, wherein said storage means (103) is a read only memory which can be previously loaded with a task instruction to be executed.
Claim 7
Dependent Claim
28 words
A counter/timer device according to Claim 5, wherein said read only memory is an erasably programmable read-only memory in which a previously loaded task instruction can be altered.
Claim 8
Dependent Claim
30 words
A counter/timer device according to Claim 5, wherein said read only memory is an electrically erasable and programmable read-only memory in which a previously loaded task instruction can be altered.
Claim 9
Dependent Claim
134 words
A counter/timer device according to Claim 1, wherein said arithmetic unit means of said counter/timer operation means (207) includes first and second source latch means (106, 107) connected to said bus means and receiving first and second data from registers which are included in said register group (105) and specified by said task instruction control means (206), an arithmetic unit (108) connected to said first and second source latch means (106, 107) for performing an arithmetic/logic operation on the basis of data from said first and second source latch means, and destination latch means (109) connected to said arithmetic unit and said bus means for writing the result of the arithmetic/logic operation performed by said arithmetic unit in a register which is specified by said task instruction control means (206), through said bus means.
Claim 10
Dependent Claim
42 words
A counter/timer device according to Claim 8, wherein said counter/timer operation means (207) further includes an output latch group (110) connected to said arithmetic unit (108) for delivering the result of an arithmetic/logic operation performed by said arithmetic unit, to the outside.
Claim 11
Dependent Claim
73 words
A counter/timer device according to Claim 9, wherein said output latch group (110) is connected to said task instruction decoding means (206), to select an output latch from said output latch group (110) in accordance with the contents of a task instruction controlled by said task instruction control means (.206), and said result of the arithmetic/logic operation performed by said arithmetic unit (108) is delivered to the outside through the selected output latch.
Claim 12
Dependent Claim
41 words
ll. A counter/timer device according to Claim 1, wherein said task instruction control means (206) further includes external signal input means (115) for selectively receiving external input signals in accordance with a task instruction from said task instruction generating means (205).
Claim 13
Dependent Claim
130 words
A counter/timer device according to Claim 10, wherein said task instruction control means (206) further includes external signal input means (115) for selectively receiving external input signals in accordance with a task instruction from said task instruction generating means (205), and wherein the counter/timer device further comprises an input/output latch group (210) for which a microcomputer unit (100) connected to said counter/timer device can perform both a writing operation and a reading operation, and input/output pin selector means (211) connected to both said output latch group (110) of said counter/timer operation means (207) and said external signal input means (115) of said task instruction control means (206) for connecting external input/output pins other than external pins used in a task instruction to be executed, to said input/output latch group (210).
Claim 14
Dependent Claim
55 words
A counter/timer device according to Claim 2, wherein each of registers included in said register group (105) of said counter/timer operation means (207) performs one of the function of a counter/timer register, the function of a capture register and the function of a compare register, under the control of said task instruction control means (206).
Claim 15
Dependent Claim
104 words
A counter/timer device according to Claim 13, wherein each of said to-be-executed task instructions stored in said storage means (103) is formed of a plurality of bits, and said bits include a bit portion for specifying a register in said register group (105) of said counter/timer operation means (207) as a register which is to function as a counter/timer register, a bit portion for specifying another register in said register group (105) as a register which is to function as one of a capture register and a compare register, and a bit portion for specifying the operation mode of each of the specified registers.
Claim 16
Dependent Claim
28 words
A counter/timer device according to Claim 1, wherein said counter/timer device is incorporated in a single-chip microcomputer together with a microcomputer unit (100) connected to the counter/timer device.
Claim 17
Dependent Claim
135 words
A single-chip microcomputer comprising: a microcomputer unit (100) including a central processing unit (200), a program storage part (202) for storing programs which are to be executed by said central processing unit, and a data storage part (201) for storing data which is used in executing said programs; and a counter/timer unit (100') connected to said microcomputer unit (100) and including task instruction generating means (205) capable of successively generating a plurality of task instructions corresponding to counter/timer operations to be carried out, one by one, task instruction control means (206) responsive to each of task instructions successively generated by said task instruction generating means, to generate a control signal, and counter/timer operation means (207) for performing a counter/timer operation corresponding to each of the successively generated task instructions, in response to said control signal.
Claim 18
Dependent Claim
135 words
A single-chip microcomputer comprising: a microcomputer unit (100) including a central processing unit (200), a program storage part (202) for storing programs which are to be executed by said central processing unit, and a data storage part (201) for storing data which is used in executing said programs; and a counter/timer unit (100') connected to said microcomputer unit (100) and including task instruction generating means (205) capable of successively generating a plurality of task instructions corresponding to counter/timer operations to be carried out, one by one, task instruction control means (206) responsive to each of task instructions successively generated by said task instruction generating means, to generate a control signal, and counter/timer operation means (207) for performing a counter/timer operation corresponding to each of the successively generated task instructions, in response to said control signal.
Claim 19
Dependent Claim
78 words
A single-chip microcomputer according to Claim 16, wherein said counter/timer operation means (207) includes a register group (105) made up of a plurality of registers each capable of performing any of plural register functions necessary for said counter/timer operations, arithmetic unit means (106 to 109) for performing an arithmetic/logic operation on the basis of data from said register group (105), and bus means (116 to 118) for transferring data between said register group and said arithmetic unit means.
Claim 20
Dependent Claim
72 words
A single-chip microcomputer according to Claim 17, wherein each of task instructions generated by said task instruction generating means (205) is formed of a plurality of bits, and said bits include bits for specifying registers in said register group (105) of said counter/timer operation means (207) as registers which are to be used in one of said task instructions, and bits for specifying the operation mode of each of the specified registers.
References Cited (Backward Citations)
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