A data processing machine for compiling computer programs

Claim 2

A data processing machine for compiling a computer program in which a particular operation may be controlled by instructions of different lengths characterised in that the machine is controlled to perform the following operation for each input computer program to be compiled; 1. defining a self contained sequence of instructions, 2. reversing the order of the sequence, 3. for each instructions that may have a different length, in turn determining the maximum register bit positions required to store the significant digits of the output that would result from executing this instruction. 4. marking the instruction to indicate this maximum length 5. replacing in the sequence any instruction found to require less register lengths than originally defined with an instruction of the appropriate definition.

Claim 3

A data processing machine for compiling a computer program in which a particular operation may be controlled by instructions of different lengths characterised in that the machine is controlled to perform the following operation for each input computer program to be compiled; 1. examining a sequential instruction stream and determining which bits of the result of each instruction could be significant, based on the context of the instruction in the instruction stream, and 2. generating the most efficient instruction form that computes the correct result in only the bit positions that were determined could be significant.

Claim 4

A data processing machine for compiling a computer program in which a particular operation may be controlled by instructions of different lengths characterised in that the machine is controlled to perform the following operation for each input computer program to be compiled; 1. examining a sequential instruction stream and determining which bits of the result of each instruction could be significant, based on the context of the instruction in the instruction stream, and 2. generating the most efficient instruction form that computes the correct result in only the bit positions that were determined could be significant.

Claim 5

A data processing machine as claimed in claim 2 in which the machine is controlled to 1. examine a linear instruction stream in reverse order and determining for each instruction those bits of the result which must be considered significant (significance value (s.v.)) and marking each input operand to that instruction to the same significance value, 2. propagate upwards in the instruction stream said input operand significance values to any instructions wherein the result of said instruction is an input operand to a subsequent instruction, 3. continue said procedure in reverse order until all of the instructions in the instruction stream have been evaluated and generating the most efficient instruction form for the entire stream for those instructions whose result significance value were changed from an "all bits significant" state by said evaluation procedure.

Claim 6

A data processing machine as claimed in claim 3 wherein real registers are assigned to each instruction and controlled to a (s.v.) memory location relating to each real system register for storing significance value data for operands to be stored in each said register, set each said (s.v.) memory location to a predetermined maximum at the beginning of said procedure, and change the significance value of a particular memory location when the operand to be stored in the related register has a significance value other than that already present.

Claim 7

A data processing machine as claimed in claim 4 further controlled after completion of an evaluation procedure, to access said (s.v.) memory at the assigned locations relating to the result of each instruction and marking said instruction with the significance value stored in said table for use in the "final code generation" phase of the compiler.

Claim 8

A data processing machine as claimed in claim 5 further controlled to determine if the use of a particular register is a "last use" in the instruction stream being evaluated before entering a significance value in the (s.v.) memory location related to said register, substitute the new value for the old value if it is a "last use," and 'OR' the new value with the old value if it is not a "last use".

Claim 9

A code optimizing method operable within an optimizing compiler after the register allocation phase thereof, said method being operable to perform significant bit analysis, the results of said analysis being utilized during the final code generation phase of the compiler operations for generating the most efficient form of computer instruction available for producing the required result said method comprising, establishing a significant bit table in memory being a storage location relating to each working register for target system and means for accessing said table at a location derivable from the register number assignment of the operands of an instruction, examining a linear code stream which is to be optimized, sequentially in reverse order, if an instruction being evaluated is a non-computational "label" obtaining the next instruction, if an instruction is a return or branch instruction setting the significance value of all of the array storage locations to "all significant" and obtaining the next instruction, determining for each computational type instruction, the maximum significance value of its result and specifying this significance value as the required significance values for its two input operands, determining the significance value for a particular result as being no greater than the significance value required for a subsequent operation to which it will become an input, and continuing the evaluation process until all of the instructions in a particular instruction stream have been processed, and marking each instruction with a significance value marker representative of the results of said significant value process.

Claim 10

A code optimizing method operable within an optimizing compiler after the register allocation phase thereof, said method being operable to perform significant bit analysis, the results of said analysis being utilized during the final code generation phase of the compiler operations for generating the most efficient form of computer instruction available for producing the required result said method comprising, establishing a significant bit table in memory being a storage location relating to each working register for target system and means for accessing said table at a location derivable from the register number assignment of the operands of an instruction, examining a linear code stream which is to be optimized, sequentially in reverse order, if an instruction being evaluated is a non-computational "label" obtaining the next instruction, if an instruction is a return or branch instruction setting the significance value of all of the array storage locations to "all significant" and obtaining the next instruction, determining for each computational type instruction, the maximum significance value of its result and specifying this significance value as the required significance values for its two input operands, determining the significance value for a particular result as being no greater than the significance value required for a subsequent operation to which it will become an input, and continuing the evaluation process until all of the instructions in a particular instruction stream have been processed, and marking each instruction with a significance value marker representative of the results of said significant value process.

Claim 11

A method as claimed in claim 7 wherein an 'add' or 'subtract' instruction is obtained and which comprises setting or adding to the significant bits of each input register all the bits at and to the right of the leftmost significant bit of the result register, in said significant bit table.

Claim 12

A method as claimed in claim 7 or claim 8 wherein the computational instruction comprises a "move register" or an "AND, OR, or EXOR" logical operation" including; setting or adding to the significant bits of each input register of the instruction, the significant bits of the result register.

Claim 13

A method as claimed in claim 7, 8 or 9 wherein the computational instruction comprises a "compare registers" operation including; setting the significant bits of each input register as "all significant."