EP0179605A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device having a serial data input circuit and a serial data output circuit
Assignee: Fujitsu Ltd
•
Filing: 1985-10-14
•
Granted: —
•
Expires: 2005-10-14
Abstract
Abstract A semiconductor memory device includes a memory cell array (1 a serial data input circuit for high-speed, large data storage in memory cells and a serial data output circuit for high-speed, large data read-out from the memory cells. The serial data input circuit includes a set (15a) of shift registers for consecutively storing serial input data (SIN) applied from an external circuit, and a set (14a) of first gates for simultaneously coupling the shift registers and a plurality of bit lines (BL) of the memory cell array to enter simultaneously the serial input data stored in the shift registers into desired memory cells selected by a desired word line. The serial data output circuit includes a set (12a) of second gates coupled to the bit lines, a set (7a) of data holding circuits, an input of each of which is connectable to the corresponding bit line through the corresponding one of the second gates, a set (11a) of third gates provided between outputs of the data holding circuits and a data bus or buses (26) and for outputting data held in the data holding circuits to the data bus or buses, and a data output circuit (9a, 10a) having a gate driving circuit for selectively driving one of the third gates. The second gates are simultaneously operated to transfer a plurality of data on a selected word line into the data holding circuit set, and the data held in the holding circuits are fed out to the data bus or buses in response to the operation of the third gates. The device can be used for high-speed, large data first-in first-out operation.
Inventors
- 👤 Junji Ogawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 09:29
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C7/00; G11C7/10; G11C7/1078; G11C7/1087; G11C11/40; G11C7/1051; G11C7/1075
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
347 words
A semiconductor memory device comprising a memory cell array (1) including a plurality of memory cells arranged in a matrix form with a plurality of bit lines (BL) and a plurality of word lines (WL); characterised by a serial data input circuit, operatively connected to the memory cell array, including one or more shift register sets (15), each having a plurality of shift registers (SR) for consecutively storing serial input data (SIN) applied from an external circuit, and one or more first gate sets (14), each having a plurality of gates for operating and simultaneously connecting the plurality of shift registers of the shift register set (15) and the plurality of bit lines (BL) to enter simultaneously the serial input data stored in the plurality of shift registers into desired memory cells in the memory cell array selected by a desired one of the word lines; and a serial data output circuit, operatively connected to the memory cell array, including one or more second gate sets (12), each having a plurality of gates operatively connected to the plurality of bit lines, one or more data holding circuit sets (7), each having a plurality of data holding circuits, an input of each of which is operatively connectable to the corresponding bit line through the corresponding gate of the second gate set, and one or more third gate sets (11), each having a plurality of gates provided between outputs of the plurality of data holding circuits and one or more data buses (26) and for outputting data held in the data holding circuits to the data buses, and data output means (9,10) having a gate driving circuit for selectively driving one of the gates in the third gate set, the plurality of gates of the second gate set being simultaneously operated to transfer a plurality of data on a selected one of the word lines into the data holding circuit set, and the data held in the holding circuit set being fed out to the data bus or buses in response to the operation of the third gate set.
Claim 2
Dependent Claim
347 words
A semiconductor memory device comprising a memory cell array (1) including a plurality of memory cells arranged in a matrix form with a plurality of bit lines (BL) and a plurality of word lines (WL); characterised by a serial data input circuit, operatively connected to the memory cell array, including one or more shift register sets (15), each having a plurality of shift registers (SR) for consecutively storing serial input data (SIN) applied from an external circuit, and one or more first gate sets (14), each having a plurality of gates for operating and simultaneously connecting the plurality of shift registers of the shift register set (15) and the plurality of bit lines (BL) to enter simultaneously the serial input data stored in the plurality of shift registers into desired memory cells in the memory cell array selected by a desired one of the word lines; and a serial data output circuit, operatively connected to the memory cell array, including one or more second gate sets (12), each having a plurality of gates operatively connected to the plurality of bit lines, one or more data holding circuit sets (7), each having a plurality of data holding circuits, an input of each of which is operatively connectable to the corresponding bit line through the corresponding gate of the second gate set, and one or more third gate sets (11), each having a plurality of gates provided between outputs of the plurality of data holding circuits and one or more data buses (26) and for outputting data held in the data holding circuits to the data buses, and data output means (9,10) having a gate driving circuit for selectively driving one of the gates in the third gate set, the plurality of gates of the second gate set being simultaneously operated to transfer a plurality of data on a selected one of the word lines into the data holding circuit set, and the data held in the holding circuit set being fed out to the data bus or buses in response to the operation of the third gate set.
Claim 3
Dependent Claim
62 words
A device according to claim 1, characterised in that the gate driving circuit in the data output means (9,10) includes a plurality of shift registers, the data held in the holding circuit set (7) being fed out on the data bus (26) through the third gate set (11) in response to the operation of the shift registers of the gate driving circuit.
Claim 4
Dependent Claim
50 words
A device according to claim 1 or claim 2, characterised in that the data buses (26) include i data bus lines, "k" being a positive number and a power of 2; and in that the gate driving circuit includes j/R shift registers, "j" being the number of the bit lines.
Claim 5
Independent Claim
51 words
A device according to any preceding claim, characterised in that the plurality of shift registers in the gate driving circuit are formed for only one bit shifting therein in response to a clock signal, a first one bit being set in a desired shift register by the data output means (9,10).
Claim 6
Independent Claim
28 words
A device according to any preceding claim, characterised in that each of the plurality of data holding circuits in each data holding circuit set (7) includes a flip-flop.
Claim 7
Dependent Claim
36 words
A device according to claim 5, characterised in that one output of each flip-flop of the data holding circuit is operatively connected to the data bus line through the gate in the third gate set (11).
Claim 8
Dependent Claim
42 words
A device according to claim 5, characterised in that complementary outputs of each flip-flop of the data holding circuit are operatively connected to a pair of data bus lines of the data buses through the gates in the third gate set (11).
Claim 9
Independent Claim
34 words
A device according to any one of claims 1-4, characterised in that each of the plurality of data holding circuits in each data holding circuit set (7) includes a capacitive element for holding data.
Claim 10
Independent Claim
83 words
A device according to any preceding claim, characterised by means (28) for counting the number of inputs of the serial input data (SIN) into the shift register set (15) and for outputting the counted value (S CNT ) to the data output means (9,10), the gate driving circuit driving one of the gates in the third gate set (11) in response to the counted value to read-out data, from first to last, stored in the memory cells, through the shift register set (15).
Claim 11
Dependent Claim
101 words
A device according to claim 9, characterised by means (29) for recording a sequence of selected word lines during the data store operation from the serial data input circuit and for selecting the word lines in response to the sequence of selected word lines during the data read operation by the serial data output circuit, the counting means (28) counting during the data store operation and outputting the counted value to the data output means (9,10), and the gate driving circuit performing the driving in response to each word line selection of the word line recording and selection means (29) .
Claim 12
Independent Claim
34 words
A device according to any preceding claim, characterised in that each of the shift register (SR) of the shift register set (15) in the serial data input circuit includes a two-phase ratio-type shift register.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.