EP0179245B1
Expired / Lapsed
EP
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Architecture for small instruction caches
Assignee: International Business Machines Corp
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Filing: 1985-09-07
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Granted: 1991-05-08
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Expires: 2005-09-07
Abstract
No abstract record available.
Inventors
- 👤 Sharad Prakash Gandhi
- 👤 Tushar Ramesh Gheewala
- 👤 Eric Paul Kronstadt
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 16:50
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804; G06F9/3806
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
279 words
An instruction memory for a microprocessor, characterized by including a branch target table (10) including a target address table (12), a next fetch address table (14), a valid entries table (16) and an instruction table (18), instruction address register means (20, 22, 24) for storing a target address generated by said microprocessor, decoder means (34) responsive to said instruction address register means for addressing all entries of a line of said branch target table (10) whenever a branch is taken, comparator means (26) connected to the outputs of said instruction register means (24) and said target address table (12) for providing an output indicative of a match between the target address and the accessed target adress table entry on said line, and instruction prefetch means (32) connected to said instruction address register means and said next fetch address table (14) and responsive to the output of said comparator mens (30) for fetching the instruction in the accessed next fetch address table (14) if said target address table entry matches the target address, otherwise for fetching the target and subsequent instructions from main memory, said next fetch address table entry for the line being updated so that it always contains the address of the instruction which follows the last valid instruction in the line and said valid entries table (16) being updated so that it always counts the number of valid instructions in the addressed branch target table line, instruction queue means (38) connected to said instruction table (18) for receiving instructions to be supplied to said microprocessor, and queue pointer register means (40) connected to said valid entry table (16) for storing pointers which address said instruction queue means.
Claim 2
Dependent Claim
137 words
The instruction memory as recited in claim 1 wherein said instruction address register means comprises, a first register (20) for storing an address having a virtual part and a fixed part, said address being the target address generated by said microprocessor, at least some of the bits in the fixed part of said address being supplied to said decoder means, address translation means (22) connected to said first register (20) and responsive to the virtual part of said target address for generating a corresponding real address, and a second register (24) connected to receive the real address from said address translation means (22) and the fixed part of said target address stored in said first register, said comparator means (26) receiving said real address stored in said second register for comparison with the accessed target address table.
Claim 3
Dependent Claim
158 words
The instruction memory as recited in claim 1, said memory being n-way set assocative and further comprising, at least a second branch target table (10₁, 10₂), a second next fetch address table (14₁, 14₂), a second valid address table (16₁, 16₂) and a second instruction table (18₁, 18₂), at least a second decoder means (34₁, 34₂) responsive to said instruction register means (24) for addressing all entries of a line of said branch target table whenever a branch is taken, at least a second comparator means (26₁, 26₂) connected to the outputs of said instruction address register means and said target address table of said second branch target table for providing an output indicative of a match between the target address and the accessed target address table entry on said accessed line, and selection means (30) controlled by the outputs of said comparators (26₁, 26₂) for providing the outputs of one of said instruction tables to said microprosessor.
Claim 4
Independent Claim
128 words
A method of operating an instruction memory for a microprosessor, said instruction memory characterized by a branch target table (10) having a target address table (12), a next fetch address table (14), a valid entries table (16) and an instruction table (18), said method comprising the steps of referencing said branch target table (10) by the addresses of instructions which are targets of branches, all entries of an addressed line of said branch target table being accessed whenever a branch is taken, comparing the target address with the target address table entry on said addressed line and, if said target address table entry matches the target address, fetching the instruction addressed by said next fetch address table entry, otherwise fetching the target and subsequent instructions from main memory.
Claim 5
Dependent Claim
74 words
The method according to claim 4 further comprising the additional steps performed when an instruction is fetched of updating the next fetch address table entry for the addressed branch target table line so that it always contains the address of the instruction which follows the last valid instruction in the line, and updating the valid entries table so that it always counts the number of valid instructions in the addressed branch target table line.
References Cited (Backward Citations)
No citation records indexed.
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