Semiconductor memory device

Claim 1

A semiconductor memory device comprising: a random access memory portion; a shift register for enabling parallel transfer of a one word line amount of data of said random access memory portion between said random access memory portion and the shift register, said shift register being divided into a plurality of shift register portions, serial input data being distributed alternately between said shift register portions by the operation of a multiplexer, serial output data being obtained by picking up data alternately from said shift register portions by the operation of another multiplexer; a transfer gate portion inserted between said random access memory portion and said shift register for carrying out parallel transfer, said transfer gate portion consisting of a plurality of groups of transfer gates for enabling selective connections of input and output terminals of each stages of said shift register portions either of the adjacent odd number bit line and even number bit line in said random access memory portion, said plurality of transfer gate groups being switched in correspondence with shift clock signals.