Data retrieving apparatus

Claim 2

A data string retrieving apparatus comprising means for receiving a string of data, a memory array having a plurality of memory locations arranged in rows and columns, said memory array being adapted to store a reference string of data, means responsive to the received string of data for sequentially selecting the rows of said memory array thereby to sequentially activate the columns of said memory array, a plurality of first storage circuits, a plurality of second storage circuits, a plurality of first gating circuits, each one of said first gating circuits being responsive to signals form one of said columns and one of said first storage circuits for transferring the content of said one first storage circuit to another one of said first storage circuits, and a · plurality of second gating circuits, each one of said second gating circuits being responsive to a signal from one of said columns for selectively transferring a logic sum of the contents of one of said first storage circuits and one of said second storage circuits to another one of said second storage circuits.

Claim 3

The apparatus according to claim 1, wherein said columns of said memory array are classified into first to n-th (n being an integer more than 2) columns, and the first gating circuit coupled to i-th (2 ≤ i ≤ n) column is adapted to transfer the content of the first storage circuit arranged for (i-l)th column to the first storage circuit arranged for i-th column.

Claim 4

The apparatus according to claim 1, wherein said columns of said memory array are classified into first to n-th (n being an integer more than 2) columns, and the second gating circuit coupled to i-th (2 ≤ i ≤ n) column is adapted to transfer the logic sum of the contents of the first storage circuit arranged for (i-l)th column and the second storage circuit arranged for (i-l)th column to the second storage circuit arranged for i-th column.

Claim 5

The apparatus according to claim 1, wherein each of said first gating circuits includes a first AND gate having a first input coupled to one of said columns, a second input coupled to an output of one of first storage circuits, and an output coupled to an input of another one of said first storage circuits.

Claim 6

The apparatus according to claim 1, wherein each of said second gating circuits includes a first AND gate having a first input coupled to one of said columns and a second input coupled to an output of one of said first storage circuits, a second AND gate having a first input coupled to said one column and a second input coupled to an output of one of said second storage circuits, and a OR gate receiving the outputs of said first and second AND gates and having an output coupled to an input of another one of said second storage circuits.

Claim 7

A string retrieving apparatus for retrieving a string of characters comprising a memory circuit having a plurality of input lines, a plurality of output lines, and a plurality of memory cells, each of said input lines corresponding to one of characters in a character string stored in said memory circuit, the output line being activated through one of said memory cells storing one logic level in response-to an activation of one of said input line coupled to said one of memory cells, means for applying a string of characters to be retrieved to said memory circuit; a first sequential logic circuit including a plurality of logic stages, the number of said logic stages being not more than the number of characters in said string, a second sequential logic circuit including a plurality of logic stages, the number of said logic stages in said second sequential logic circuit being less than that in said first sequential logic circuit, first control means for controlling said first sequential logic circuit in response to logic state of said output lines, and second control means for controlling said second sequential logic circuit in response to logic state of said output lines.

Claim 8

A string retrieving apparatus for retrieving a string of characters comprising a memory circuit having a plurality of input lines, a plurality of output lines, and a plurality of memory cells, each of said input lines corresponding to one of characters in a character string stored in said memory circuit, the output line being activated through one of said memory cells storing one logic level in response-to an activation of one of said input line coupled to said one of memory cells, means for applying a string of characters to be retrieved to said memory circuit; a first sequential logic circuit including a plurality of logic stages, the number of said logic stages being not more than the number of characters in said string, a second sequential logic circuit including a plurality of logic stages, the number of said logic stages in said second sequential logic circuit being less than that in said first sequential logic circuit, first control means for controlling said first sequential logic circuit in response to logic state of said output lines, and second control means for controlling said second sequential logic circuit in response to logic state of said output lines.

Claim 9

A string collation apparatus comprising: string memory means for receiving symbol codes as address inputs and storing a collation string; a plurality of first transmission means each connected to each output of said string memory means; and a register array which contains M-row and N-column (M ≤ N) registers in which adjacent registers of the Nth row are connected to said first transmission means; and a plurality of second transmission means each for connecting the register at the position of an Ith (1 ≤ I ≤ M) row and a Jth (1 ≤ J ≤ N) column in said register array to the registers at the position of an (I + l)th row and Jth column and at the position of the (I + l)th row and (J + l)th column.

Claim 10

A string collation apparatus comprising: string memory means for receiving symbol codes as address inputs and storing a collation string; a plurality of first transmission means each connected to each output of said string memory means; and a register array which contains M-row and N-column (M ≤ N) registers in which adjacent registers of the Nth row are connected to said first transmission means; and a plurality of second transmission means each for connecting the register at the position of an Ith (1 ≤ I ≤ M) row and a Jth (1 ≤ J ≤ N) column in said register array to the registers at the position of an (I + l)th row and Jth column and at the position of the (I + l)th row and (J + l)th column.