Subband encoding method and apparatus

Claim 2

In a crytographic digital signal transceiver including means for processing an input electrical signal having a frequency band of signal components by separating it into plural frequency subbands of signal components which subbands are separately encoded into corresponding binary-valued digital signals that are subsequently combined for transmission over a common digital communication channel, the improvement comprising: hybrid encoding means which encodes the signal components of at least one of said subbands in accordance with a first predetermined encoding algorithm and which encodes the signal components of at least one other of said subbands in accordance with a different second predetermined encoding algorithm; time delay means operating in at least one of said subbands to time delay said digital signals in the encoded bit-compressed digital format so as to provide time delay while reducing digital memory requirements for effecting such time delay; and control means for formatting the digital data being transmitted over said common communication channel to include cryptographic synchronization and frame synchronization signals recurrently during an ongoing transmission whereby late entry receipt of the transmitted digital data is facilitated.

Claim 3

An improved cryptographic digital signal transceiver as in Claim 1 wherein said hybrid encoding means includes APCM means for effecting adaptive pulse code modulation as said first predetermined encoding algorithm and BCPCM means for effecting block companded pulse code modulation as said second predetermined encoding algorithm.

Claim 4

An improved cryptographic digital signal transceiver as in Claim 1 including: QMF filter means for separating a digitized input signal into plural subbands of digital signals having different respective time delays therein and representing corresponding subbsnds of signal frequency components; said hybrid encoding coding means separately coding the digital signals in each subband in a digitally compressed form to provide compressed coded digital signals in each of said subbands; said time delay means time delaying said compressed coded digital signals in at least one of said subbands for a predetermined time period to provide substantially time synchronous digital signals at a predetermined point in each of said subbands; and multiplex means for combining said substantially time synchronous digital signals into an output stream of coded compressed digital signals.

Claim 5

An improved cryptographic digital signal transceiver as in Claim 1 including: transmitter and receiver means for transmitting and/or receiving a succession of digital signals; and wherein said control means is connected to said transmitter and receiver means and includes a digital data microprocessor system programmed so as to perform the following functions: (a) initial synchronization acquisition wherein said received digital signals are scanned for an initial preamble portion from which frame synchronization, addressing and cryptographic synchronization signals are extracted, (b) ongoing synchronization maintenance wherein said received digital signals are scanned for data frames succeeding said preamble portion and from which data frames at least said frame synchronization and said cryptographic synchronization signals are repeatedly extracted so as to permit maintenance of such synchronization throughout the decoding of an encrypted message comprising plural such data frames, and (c) late entry wherein, in the event frame synchronization and/or cryptographic synchronization are lost or not acquired from said preamble, said data frames are scanned and from which synchronization, addressing and cryptographic synchronization signals are nevertheless extracted and control passed back to said ongoing synchronization maintenance function such that the remaining portion of a properly addressed encrypted message data stream is nevertheless successfully decoded.

Claim 6

A transceiver for sending and receiving digitized and cryptographically encrypted data signals over a communication channel, said transceiver comprising: receiver means for providing a sequence of received digital signals; transmitter means for transmitting a sequence of generated digital signals; and ditigal signal processing and control means connected to said receiver means and to said transmitter means for processing said received digital signals into audio output and for generating said generated digital signals from audio signals input thereto, said digital signal processing and control means effecting hybrid subband encoding/decoding of said digital signals by dividing them into plural subbands and by using a different encoding/decoding algorithm in at least one subband than the encoding/decoding algorithm used in at least one other subband; and wherein both said received and said generated digital signals are formatted to include (a) an initial preamble portion which includes timing synchronization signals and cryptographic synchronization signals, and (b) a subsequent sequence of frames of encrypted data also including embedded timing synchronization signals and embedded crytographic synchronization signals; said digital signal processing means being adapted to automatically detect and monitor said embedded synchronization signals within said received digital signals so as to maintain accurate timing and crytographic synchronization data and so as to establish accurate timing and cryptographic synchronization even after occurrence of said preamble portion in the event of belated signal reception or temporary loss of accurate synchronization data during the course of a given received message.

Claim 7

A transceiver for sending and receiving digitized and cryptographically encrypted data signals over a communication channel, said transceiver comprising: receiver means for providing a sequence of received digital signals; transmitter means for transmitting a sequence of generated digital signals; and ditigal signal processing and control means connected to said receiver means and to said transmitter means for processing said received digital signals into audio output and for generating said generated digital signals from audio signals input thereto, said digital signal processing and control means effecting hybrid subband encoding/decoding of said digital signals by dividing them into plural subbands and by using a different encoding/decoding algorithm in at least one subband than the encoding/decoding algorithm used in at least one other subband; and wherein both said received and said generated digital signals are formatted to include (a) an initial preamble portion which includes timing synchronization signals and cryptographic synchronization signals, and (b) a subsequent sequence of frames of encrypted data also including embedded timing synchronization signals and embedded crytographic synchronization signals; said digital signal processing means being adapted to automatically detect and monitor said embedded synchronization signals within said received digital signals so as to maintain accurate timing and crytographic synchronization data and so as to establish accurate timing and cryptographic synchronization even after occurrence of said preamble portion in the event of belated signal reception or temporary loss of accurate synchronization data during the course of a given received message.

Claim 8

A transceiver as in Claim 5 wherein said digital signal processing and control means processes digital signals which include addressing signals identifying the desired message recipient both in said initial preamble portion and embedded in said frames of encrypted data, said digital signal processing means also being adapted to automatically detect and monitor said embedded address signals so as to enable belated correctly addressed receipt of a message even after occurrence of said preamble portion in the event of belated signal reception or temporary loss of accurate address data during the course of a given received message.

Claim 9

In a subband signal processing method for processing input electrical signals having a frequency band of signal components by separation into plural frequency subbands of signal components which subbands are separately encoded into corresponding binary-valued digital signals that are subsequently combined for transmission over a common digital communication channel, the improvement comprising: (a) encoding the signal components of at least one of said subbands in accordance with a first predetermined encoding algorithm and encoding the signal components of at least one other of said subbands in accordance with a different second predetermined encoding algorithm; (b) time delaying said digital signals in a bit-compressed encoded digital format in at least one said subband so as to provide time delay while reducing digital memory requirements for effecting such time delay; (c) scanning received signals for an initial preamble portion from which frame synchronization, addressing and cryptographic synchronization signals are extracted, (d) scanning said received digital signals for data frames succeeding said preamble portion and from which data frames at least said frame synchronization and said cryptographic synchronization signals are repeatedly extracted so as to permit maintenance of such synchronization throughout the decoding of an encrypted message comprising plural such data frames, and (e) in the event frame synchronization and/or cryptographic synchronization are lost or not acquired from said preamble, scanning said data frames from which synchronization, addressing and cryptographic synchronization signals are nevertheless extracted and control is passed back to said ongoing synchronization maintenance function such that the remaining portion of a properly addressed encrypted voice message data stream is nevertheless successfully decoded.

Claim 10

In a subband signal processing method for processing input electrical signals having a frequency band of signal components by separation into plural frequency subbands of signal components which subbands are separately encoded into corresponding binary-valued digital signals that are subsequently combined for transmission over a common digital communication channel, the improvement comprising: (a) encoding the signal components of at least one of said subbands in accordance with a first predetermined encoding algorithm and encoding the signal components of at least one other of said subbands in accordance with a different second predetermined encoding algorithm; (b) time delaying said digital signals in a bit-compressed encoded digital format in at least one said subband so as to provide time delay while reducing digital memory requirements for effecting such time delay; (c) scanning received signals for an initial preamble portion from which frame synchronization, addressing and cryptographic synchronization signals are extracted, (d) scanning said received digital signals for data frames succeeding said preamble portion and from which data frames at least said frame synchronization and said cryptographic synchronization signals are repeatedly extracted so as to permit maintenance of such synchronization throughout the decoding of an encrypted message comprising plural such data frames, and (e) in the event frame synchronization and/or cryptographic synchronization are lost or not acquired from said preamble, scanning said data frames from which synchronization, addressing and cryptographic synchronization signals are nevertheless extracted and control is passed back to said ongoing synchronization maintenance function such that the remaining portion of a properly addressed encrypted voice message data stream is nevertheless successfully decoded.

Claim 11

A method as in Claim 7 wherein said digital signals occur in substantially the following time sequence for a complete message (A) a preamble portion having: (1) an alternating 1.0 data pattern, (2) 12 repeated sets of (i) a 16 bit synchronization word including a multiple bit Barker code, (ii) a 16 bit outside address word including a multiple bit address repeated at least once in complemented form, (iii) a 16 bit sync number code including a multiple bit number code (identifying which of the 12 repeats is involved) repeated at least once and also including at least 1 bit of parity code, (3) 9 repeated sets of (i) a 64 bit guard band, (ii) a 64 bit cryptographic initialization vector, (iii) a 16 bit selective signalling code identifying the intended message recipient(s), (B) successive data frames which each include (1) a 112 bit header portion having (i) a 16 bit synchronization word including a multiple bit Barker code, (ii) a 16 bit outside address word including a multiple bit address repeated at least once, (iii) a 16 bit selective signalling code identifying the intended message recipient(s), (iv) a 64 bit cryptographic initialization vector, (v) at least one of the bit fields in the header portion being distinguishable from the respectively corresponding field in the preamble so as to permit detection of a late entry condition, (2) a 2040 bit string of cryptographically encoded digital data, and (C) an end-of-message word signifying the end of a given message.

Claim 12

An improved subband signal processing method as in Claim 7 wherein adaptive pulse code modulation is used as said first predetermined encoding algorithm and block companded pulse code modulation is used as said second predetermined encoding algorithm.

Claim 15

A method as in Claim 10 wherein said digital signals include addressing signals identifying the desired message recipient both in said initial preamble portion and embedded in said frames of encrypted data, and automatically detecting and monitoring said embedded address signals so as to enable belatedly correctly addressed receipt of a message even after occurrence of said preamble portion in the event of belated signal reception or temporary loss of accurate address data during the course of a given received message.

Claim 16

A method as in Claim 10 further comprising the step of time delaying said digitally band compressed signals in at least one of said subbands so as to reduce the digital memory requirements for effecting such time delay.

Claim 17

In a subband coder including means for processing an input electrical signal having a frequency band of signal components by separating it into plural frequency subbands of signal components which subbands are separately encoded into corresponding binary-valued digital signals that are subsequently combined for transmission over a common digital communication channel, the improvement comprising: hybrid encoding means which encodes the signal components of at least one of said subbands in accordance with a first predetermined encoding algorithm and which encodes the signal components of at least one other of said subbands in accordance with a different second predetermined encoding algorithm.

Claim 18

In a subband coder including means for processing an input electrical signal having a frequency band of signal components by separating it into plural frequency subbands of signal components which subbands are separately encoded into corresponding binary-valued digital signals that are subsequently combined for transmission over a common digital communication channel, the improvement comprising: hybrid encoding means which encodes the signal components of at least one of said subbands in accordance with a first predetermined encoding algorithm and which encodes the signal components of at least one other of said subbands in accordance with a different second predetermined encoding algorithm.

Claim 19

An improved subband coder as in Claim 13 wherein said hybrid encoding means includes APCM means for effecting adaptive pulse code modulation as said first predetermined encoding algorithm and BCPCM means for effecting block companded pulse code modulation as said second predetermined encoding algorithm.

Claim 20

A hybrid subband electrical signal processor comprising: filter means having an input for accepting digital electrical signals representing a band of frequency components and having plural outputs each producing digital subband signals representing signal components of the input electrical signal within different frequency subbands; first digital encoder means for receiving the digital subband signals from one of said outputs and for encoding same in accordance with a first predetermined encoding algorithm to produce first encoded digital signals; second digital encoder means for receiving the digital subband signals from another of said outputs and for encoding same in accordance with a different second predetermined encoding algorithm to produce second encoded digital signals; and multiplex means for combining said first and second encoded digital signals into a common string of digital signals for transmission over a digital signal communication channel.

Claim 21

A hybrid subband electrical signal processor comprising: filter means having an input for accepting digital electrical signals representing a band of frequency components and having plural outputs each producing digital subband signals representing signal components of the input electrical signal within different frequency subbands; first digital encoder means for receiving the digital subband signals from one of said outputs and for encoding same in accordance with a first predetermined encoding algorithm to produce first encoded digital signals; second digital encoder means for receiving the digital subband signals from another of said outputs and for encoding same in accordance with a different second predetermined encoding algorithm to produce second encoded digital signals; and multiplex means for combining said first and second encoded digital signals into a common string of digital signals for transmission over a digital signal communication channel.

Claim 22

A hybrid subband electrical signal processor as in Claim 15 wherein: said first encoder means uses an APCM encoding algorithm and said second encoder means uses a BCPCM encoding algorithm.

Claim 23

A hybrid subband electrical signal processor as in Claim 15 further comprising: demultiplex means for separating an incoming bit-serial string of digital signals into plural subband channels having therein encoded incoming digital signals representing signal components within different frequency subbands; first digital decoder means for receiving said encoded incoming digital signals in at least one of said subband channels and producing decoded incoming digital signals therefrom in accordance with a first predetermined decoding algorithm; second digital decoder means for receiving said encoded incoming digital signals in at least one other of said subband channels and producing decoded incoming digital signals therefrom in accordance with a second predetermined decoding algorithm; and inverse filter means for accepting said decoded incoming digital signals from each subband channel and for producing a decoded string of digital signals.

Claim 24

In a subband signal processing method for processing an input electrical signal having a frequency band of signal components by separating it into plural frequency subbands of signal components which subbands are separately encoded into corresponding binary-valued digital signals that are subsequently combined for transmission over a common digital communication channel, the improvement comprising: encoding the signal components of at least one of said subbands in accordance with a first predetermined encoding algorithm and encoding the signal components of at least one other of said subbands in accordance with a different second predetermined encoding algorithm.

Claim 25

In a subband signal processing method for processing an input electrical signal having a frequency band of signal components by separating it into plural frequency subbands of signal components which subbands are separately encoded into corresponding binary-valued digital signals that are subsequently combined for transmission over a common digital communication channel, the improvement comprising: encoding the signal components of at least one of said subbands in accordance with a first predetermined encoding algorithm and encoding the signal components of at least one other of said subbands in accordance with a different second predetermined encoding algorithm.

Claim 26

An improved subband signal processing method as in Claim 18 wherein adaptive pulse code modulation is used as said first predetermined encoding algorithm and block companded pulse code modulation is used as said second predetermined encoding algorithm.

Claim 27

A hybrid subband electrical signal processing method comprising: accepting digital electrical signals representing a band of frequency components and producing plural outputs each having digital subband signals representing signal components of the input electrical signal within different frequency subbands; receiving the digital subband signals from one of said outputs and encoding same in accordance with a first predetermined encoding algorithm to produce first encoded digital signals; receiving the digital subband signals from another of said outputs and encoding same in accordance with a different second predetermined encoding algorithm to produce second encoded digital signals; and combining said first and second encoded digital signals into a common string of digital signals for transmission over a digital signal communication channel.

Claim 28

A hybrid subband electrical signal processing method comprising: accepting digital electrical signals representing a band of frequency components and producing plural outputs each having digital subband signals representing signal components of the input electrical signal within different frequency subbands; receiving the digital subband signals from one of said outputs and encoding same in accordance with a first predetermined encoding algorithm to produce first encoded digital signals; receiving the digital subband signals from another of said outputs and encoding same in accordance with a different second predetermined encoding algorithm to produce second encoded digital signals; and combining said first and second encoded digital signals into a common string of digital signals for transmission over a digital signal communication channel.

Claim 29

A hybrid subband electrical signal processing method as in Claim 20 wherein: an APCM encoding algorithm and a BCPCM encoding algorithm are simultaneously used in respective ones of said receiving steps.

Claim 30

A hybrid subband electrical signal processing method as in Claim 20 further comprising: separating an incoming string of digital signals into plural subband channels having therein encoded incoming digital signals representing signal components within. different frequency subbands; receiving said encoded incoming digital signals in at least one of said subband channels and producing decoded incoming digital signals therefrom in accordance with a first predetermined decoding algorithm; receiving said encoded incoming digital signals in at least one other of said subband channels and producing decoded incoming digital signals therefrom in accordance with a second predetermined decoding algorithm; and accepting said decoded incoming digital signals from each subband channel and for producing a decoded string of digital signals.

Claim 31

A transceiver for sending and receiving digital control and cryptographically encoded digital data signals over a communication channel, said transceiver comprising: transmitter and receiver means for transmitting and/or receiving a succession of digital signals; and control means connected to said transmitter and receiver means and including a digital data microprocessor system programmed so as to perform the following functions: (a) initial synchronization acquisition wherein said received digital signals are scanned for an initial preamble portion from which frame synchronization, addressing and cryptographic synchronization signals are extracted, (b) ongoing synchronization maintenance wherein said received digital signals are scanned for data frames succeeding said preamble portion and from which data frames at least said frame synchronization and said cryptographic synchronization signals are repeatedly extracted so as to permit maintenance of such synchronization throughout the decoding of an encrypted message comprising plural such data frames, and (c) late entry wherein, in the event frame synchronization and/or cryptographic synchronization are lost or not acquired from said preamble, said data frames are scanned and from which synchronization, addressing and cryptographic synchronization signals are nevertheless extracted and control passed back to said ongoing synchronization maintenance function such that the remaining portion of a properly addressed encrypted message data stream is nevertheless successfully decoded.

Claim 32

A transceiver for sending and receiving digital control and cryptographically encoded digital data signals over a communication channel, said transceiver comprising: transmitter and receiver means for transmitting and/or receiving a succession of digital signals; and control means connected to said transmitter and receiver means and including a digital data microprocessor system programmed so as to perform the following functions: (a) initial synchronization acquisition wherein said received digital signals are scanned for an initial preamble portion from which frame synchronization, addressing and cryptographic synchronization signals are extracted, (b) ongoing synchronization maintenance wherein said received digital signals are scanned for data frames succeeding said preamble portion and from which data frames at least said frame synchronization and said cryptographic synchronization signals are repeatedly extracted so as to permit maintenance of such synchronization throughout the decoding of an encrypted message comprising plural such data frames, and (c) late entry wherein, in the event frame synchronization and/or cryptographic synchronization are lost or not acquired from said preamble, said data frames are scanned and from which synchronization, addressing and cryptographic synchronization signals are nevertheless extracted and control passed back to said ongoing synchronization maintenance function such that the remaining portion of a properly addressed encrypted message data stream is nevertheless successfully decoded.

Claim 33

A transceiver for sending and receiving digitized and cryptographically encrypted data signals over a communication channel, said transceiver comprising: receiver means for providing a sequence of received digital signals; transmitter means for transmitting a sequence of generated digital signals; and digital signal processing means connected to said receiver means and to said transmitter means for processing said received digital signals into audio output and for generating said generated digital signals from audio signals input thereto, wherein both said received and said generated digital signals are formatted to include (a) an initial preamble portion which includes timing synchronization signals and cryptographic synchronization signals, and (b) a subsequent sequence of frames of encrypted data also including embedded timing synchronization signals and embedded cryptographic synchronization signals; said digital signal processing means being adapted to automatically detect and monitor said embedded synchronization signals within said received digital signals so as to maintain accurate timing and cryptographic synchronization data and so as to establish accurate timing and cryptographic synchronization even after occurrence of said preamble portion in the event of belated signal reception or temporary loss of accurate synchronization data during the course of a given received message.

Claim 34

A transceiver for sending and receiving digitized and cryptographically encrypted data signals over a communication channel, said transceiver comprising: receiver means for providing a sequence of received digital signals; transmitter means for transmitting a sequence of generated digital signals; and digital signal processing means connected to said receiver means and to said transmitter means for processing said received digital signals into audio output and for generating said generated digital signals from audio signals input thereto, wherein both said received and said generated digital signals are formatted to include (a) an initial preamble portion which includes timing synchronization signals and cryptographic synchronization signals, and (b) a subsequent sequence of frames of encrypted data also including embedded timing synchronization signals and embedded cryptographic synchronization signals; said digital signal processing means being adapted to automatically detect and monitor said embedded synchronization signals within said received digital signals so as to maintain accurate timing and cryptographic synchronization data and so as to establish accurate timing and cryptographic synchronization even after occurrence of said preamble portion in the event of belated signal reception or temporary loss of accurate synchronization data during the course of a given received message.

Claim 35

A transceiver as in Claim 24 wherein said digital signal processing means processes digital signals which include addressing signals identifying the desired message recipient both in said initial preamble portion and embedded in said frames of encrypted data, said digital signal processing Means also being adapted to automatically detect and monitor said embedded address signals so as to enable belated correctly addressed receipt of a message even after occurrence of said preamble portion in the event of belated signal reception or temporary loss of accurate address data during the course of a given received message.

Claim 36

In a radio communication system for processing digitized and cryptographically encoded signals, an improved method of formatting such digital signals, said improved method comprising the steps of processing in timed sequence the below-identified digital signals: (A) a preamble portion having: (1) an alternating 1.0 data pattern, (2) 12 repeated sets of (i) a 16 bit synchronization word including an 11 bit Barker code, (ii) a 16 bit outside address word including an 8 bit address repeated once in complemented form, (iii) a 16 bit sync number code including a 5 bit number code (identifying which of the 12 repeats is involved) repeated 3 times with the second repeat being in complemented form and also including 1 bit of odd parity code, (3) 9 repeated sets of (i) a 64 bit guard band, (ii) a 64 bit cryptographic initialization vector, (iii) a 16 bit selective signalling code identifying the intended message recipient(s), (B) successive data frames which each include (1) a 112 bit header portion having (i) a 16 bit synchronization word including an 11 bit Barker code, (ii) a 16 bit outside address word including an 8 bit address repeated once, (iii) a 16 bit selective signalling code identifying the intended.message recipient(s), (iv) a 64 bit cryptographic initialization vector, (2) a 2040 bit string of cryptographically encoded digital data, and (C) an end-of-message word signifying the end of a given message.

Claim 37

In a radio communication system for processing digitized and cryptographically encoded signals, an improved method of formatting such digital signals, said improved method comprising the steps of processing in timed sequence the below-identified digital signals: (A) a preamble portion having: (1) an alternating 1.0 data pattern, (2) 12 repeated sets of (i) a 16 bit synchronization word including an 11 bit Barker code, (ii) a 16 bit outside address word including an 8 bit address repeated once in complemented form, (iii) a 16 bit sync number code including a 5 bit number code (identifying which of the 12 repeats is involved) repeated 3 times with the second repeat being in complemented form and also including 1 bit of odd parity code, (3) 9 repeated sets of (i) a 64 bit guard band, (ii) a 64 bit cryptographic initialization vector, (iii) a 16 bit selective signalling code identifying the intended message recipient(s), (B) successive data frames which each include (1) a 112 bit header portion having (i) a 16 bit synchronization word including an 11 bit Barker code, (ii) a 16 bit outside address word including an 8 bit address repeated once, (iii) a 16 bit selective signalling code identifying the intended.message recipient(s), (iv) a 64 bit cryptographic initialization vector, (2) a 2040 bit string of cryptographically encoded digital data, and (C) an end-of-message word signifying the end of a given message.

Claim 40

A method as in Claim 27 wherein said digital signals occur in substantially the following time sequence for a complete message (A) a preamble portion having: (1) an alternating 1.0 data pattern, (2) 12 repeated sets of (i) a 16 bit synchronization word including a multiple bit Barker code, (ii) a 16 bit cutside address word including a multiple bit address repeated at least once in complemented form, (iii) a 16 bit sync number code including a multiple bit number code (identifying which of the 12 repeats is involved) repeated at least once and also including at least 1 bit of parity code, (3) 9 repeated sets of (i) a 64 bit guard band, (ii) a 64 bit cryptographic initialization vector, (iii) a 16 bit selective signalling code identifying the intended message recipient(s), (B) successive data frames which each include (1) a 112 bit header portion having (i) a 16 bit synchronization word including a multiple bit Barker code, (ii) a 16 bit outside address word including a multiple bit address repeated at least once, (iii) a 16 bit selective signalling code identifying the intended message recipient(s), (iv) a 64 bit cryptographic initialization vector, (v) at least one of the bit fields in the header portion being distinguishable from the respectively corresponding field in the preamble so as to permit detection of a late entry condition, (2) a 2040 bit string of cryptographically encoded digital data, and (C) an end-of-message word signifying the end of a given message.

Claim 43

A method as in Claim 29 wherein said digital signals include addressing signals identifying the desired message recipient both in said initial preamble portion and embedded in said frames of encrypted data, and automatically detecting and monitoring said embedded address signals so as to enable belated correctly addressed receipt of a message even after occurrence of said preamble portion in the event of belated signal reception or temporary loss of accurate address data during the course of a given received message.

Claim 44

In a digital time delay compensated signal processor using a non-symmetrical QMF filter technique to define plural subband channels of digital signals which are coded into a bit-compressed digital format for transmission over a communication channel, the improvement comprising: time delay compensation means operating in said subband channels to time delay said digital signals in the bit-compressed digital format so as to compensate for unequal time delays encountered in said non-symmetrical QMF filter technique while also minimizing digital memory requirements for effecting such time delay compensation.

Claim 45

In a digital time delay compensated signal processor using a non-symmetrical QMF filter technique to define plural subband channels of digital signals which are coded into a bit-compressed digital format for transmission over a communication channel, the improvement comprising: time delay compensation means operating in said subband channels to time delay said digital signals in the bit-compressed digital format so as to compensate for unequal time delays encountered in said non-symmetrical QMF filter technique while also minimizing digital memory requirements for effecting such time delay compensation.

Claim 46

A digital time delay compensated subband signal processor comprising: QMF filter means for separating a digitized input signal into plural subband channels of digital signals having different respective time delays therein and representing corresponding subbands of signal frequency components; digital coding means for separately coding the digital signals in each subband channel in a digitally compressed form to provide compressed coded digital signals in each of said subband channels; time delay compensation means for temporarily time delaying said compressed coded digital signals in at least one of said subband channels for a predetermined time period to provide substantially time synchronous digital signals in each of said subband channels; and multiplex means for combining said substantially time synchronous digital signals into a commoh bit-serial output stream of coded compressed digital signals.

Claim 47

A digital time delay compensated subband signal processor comprising: QMF filter means for separating a digitized input signal into plural subband channels of digital signals having different respective time delays therein and representing corresponding subbands of signal frequency components; digital coding means for separately coding the digital signals in each subband channel in a digitally compressed form to provide compressed coded digital signals in each of said subband channels; time delay compensation means for temporarily time delaying said compressed coded digital signals in at least one of said subband channels for a predetermined time period to provide substantially time synchronous digital signals in each of said subband channels; and multiplex means for combining said substantially time synchronous digital signals into a commoh bit-serial output stream of coded compressed digital signals.

Claim 48

A digital time delay compensated subband signal processor as in Claim 32 further comprising: demultiplexing means for separating a received bit-serial input stream of said coded compressed digital signals into plural received subband channels of received digital signals; second time delay compensation means for temporarily time delaying said received digital signals in at least one of said received subband channels by a predetermined time period; decoding means for separately decoding the time-delayed digital signals in each received subband channel to provide an expanded set of digital signals therein; and inverse QMF filter means for combining said expanded digital signals from each received subband channel with differing respective time delays which, in combination with the time delays introduced by said second time delay compensation means produces a time synchronous single bit-serial output stream of decoded expanded digital signals.

Claim 49

A digital time delay compensated signal processor comprising: demultiplexing means for separating a received bit-serial input stream of coded compressed digital signals into plural received subband channels of received digital signals; time delay compensation means for temporarily time delaying said received digital signals in at least one of said received subband channels by a predetermined time period; decoding means for separately decoding the time-delayed digital signals to provide an expanded set of digital signals therein; and inverse QMF filter means for combining said expanded digital signals from each received subband channel with differing respective time delays to produce a time synchronous single bit-serial output stream of decoded expanded digital signals.

Claim 50

A digital time delay compensated signal processor comprising: demultiplexing means for separating a received bit-serial input stream of coded compressed digital signals into plural received subband channels of received digital signals; time delay compensation means for temporarily time delaying said received digital signals in at least one of said received subband channels by a predetermined time period; decoding means for separately decoding the time-delayed digital signals to provide an expanded set of digital signals therein; and inverse QMF filter means for combining said expanded digital signals from each received subband channel with differing respective time delays to produce a time synchronous single bit-serial output stream of decoded expanded digital signals.

Claim 51

In a digital time delay compensated signal processing method using a non-symmetrical QMF filter technique to define plural subband channels of digital signals which are coded into a bit-compressed digital format for transmission over a communication channel, the improvement comprising: time delaying said digital signals in the bit-compressed digital format in said subband channels so as to compensate for unequal time delays encountered in said non-symmetrical QMF filter technique while also minimizing digital memory requirements for effecting such time delay compensation.

Claim 52

In a digital time delay compensated signal processing method using a non-symmetrical QMF filter technique to define plural subband channels of digital signals which are coded into a bit-compressed digital format for transmission over a communication channel, the improvement comprising: time delaying said digital signals in the bit-compressed digital format in said subband channels so as to compensate for unequal time delays encountered in said non-symmetrical QMF filter technique while also minimizing digital memory requirements for effecting such time delay compensation.

Claim 53

A digital time delay compensated subband signal processing method comprising: separating a digitized input signal into plural subband channels of digital signals having different respective time delays therein and representing corresponding subbands of signal frequency components; separately coding the digital signals in each subband channel in a digitally compressed form to provide compressed coded digital signals in each of said subband channels; temporarily time delaying said compressed coded digital signals in at least one of said subband channels for a predetermined time period to provide substantially time synchronous digital signals in each of said subband channels; and combining said substantially time synchronous digital signals into a common bit-serial output stream of coded compressed digital signals.

Claim 54

A digital time delay compensated subband signal processing method comprising: separating a digitized input signal into plural subband channels of digital signals having different respective time delays therein and representing corresponding subbands of signal frequency components; separately coding the digital signals in each subband channel in a digitally compressed form to provide compressed coded digital signals in each of said subband channels; temporarily time delaying said compressed coded digital signals in at least one of said subband channels for a predetermined time period to provide substantially time synchronous digital signals in each of said subband channels; and combining said substantially time synchronous digital signals into a common bit-serial output stream of coded compressed digital signals.

Claim 55

A digital time delay compensated subband signal processing method as in Claim 36 further comprising: separating a received bit-serial input stream of said coded compressed digital signals into plural received subband channels of received digital signals; temporarily time delaying said received digital signals in at least one of said received subband channels by a predetermined time period; separately decoding the time-delayed digital signals in each received subband channel to provide an expanded set of digital signals therein; and combining said expanded digital signals from each received subband channel with differing respective time delays which, in combination with the time delays introduced by said second time delay compensation means produces a time synchronous single bit-serial output stream of decoded expanded digital signals.

Claim 56

A digital time delay compensated signal processing method comprising: separating a received bit-serial input stream of coded compressed digital signals into plural received subband channels of received digital signals; temporarily time delaying said received digital signals in at least one of said received subband channels by a predetermined time period; separately decoding the time-delayed digital signals to provide an expanded set of digital signals therein; and combining said expanded digital signals from each received subband channel with differing respective time delays to produce a time synchronous single bit-serial output stream of decoded expanded digital signals.

Claim 57

A digital time delay compensated signal processing method comprising: separating a received bit-serial input stream of coded compressed digital signals into plural received subband channels of received digital signals; temporarily time delaying said received digital signals in at least one of said received subband channels by a predetermined time period; separately decoding the time-delayed digital signals to provide an expanded set of digital signals therein; and combining said expanded digital signals from each received subband channel with differing respective time delays to produce a time synchronous single bit-serial output stream of decoded expanded digital signals.