Process of making dual well CMOS semiconductor structure

Claim 1

A process of fabricating an integrated circuit having both P-well and N-well regions in a single semiconductor body, which process uses only a single lithographic masking step to define the positions of both of said well regions and also the position of doped field regions for controlling the parasitic threshold voltages of portions of said body, character-Led by a) forming a first electrically insulating layer (10) on a surface of said semiconductor body ( 1 2); b) forming on said first layer (10) a second electrically insulating layer (14) from a material preselected to be impervious to oxygen diffusion therethrough; c) lithographically forming a mask ( 1 6) over said second electrically insulating layer (14) to define the position of said N-well regions (20) by exposed areas in the mask, and removing said second electrically insulating layer (14) from said exposed areas; d) implanting N-type conductivity-determining impurities in said semiconductor body (12), using said mask (16) as an implantation mask to prevent implantation of said P-well regions (24); e) removing the mask; f) annealing said semiconductor body to form the desired doping profiles in said N-well regions, and oxidizing said body to convert only the body portion in said N-well regions into an electrically insulating grown oxide layer, thus forming a step in said body for use as an alignment mark; g) implanting said first insulating layer 10) with P-type conductivity determining impurities, using the grown oxide layer (29) over the N-well regions (26) as a mask; and using said second electrically insulating layer (14) over said P-well regions (28) as an etching mask for removing the insulating and oxide layers (29) from over said N-well regions (26); and h) forming a new electrically insulating layer (32) over said N-well regions (26), and implanting N-type conductivity determining impurities in said new electrically insulating layer (32) over said N-well regions (26) using said second electrically insulating layer ( 1 4) over said P-wells (28) as a masking layer to prevent said N-type conductivity determining impurities from reaching said first insulating layer portion (10) positioned over said P-well regions (28); thereby producing N- and P-well regions (26, 28) in said body (12) with alignment marks (30) on the surface of said body indicating the separation of said regions (26, 28) and with corresponding field-doped insulating layers (32, 10) over said regions, wherein the doped insulating layer (32) over said N-well regions (26) is doped with predominantly N-type impurities, and the doped insulation layer (10) over said P-well regions (28) is doped with predominantly P-type impurities.