Process for the fabrication of a nonvolatile memory cell with very small thin oxide area and cell obtained by said process

Abstract

Abstract On the doped area (7) of a monocrystalline silicium substrate (1) is grown a thick oxide layer (8) a side portion of which is subjected to etching and underetching within a predetermined area until it uncovers an edge of silicium (12) on which is then grown thin oxide (13); polycrystalline silicium layers (14, 16) separated by an oxide layer (15) are then deposited to produce a nonvolatile memory cell in which the floating gate consisting of one (14) of said polycrystalline silicium of one (14) of said polycristalline silicium layers is separated from the underlying doped area (7) of the substrate, which constitutes the drain, by a very small thin oxide area (13) which adjoins an extended area of thick oxide (8). The electrical capacitance between the floating gate (14) and the drain (7) is thus reduced with resulting smaller dimensions of the cell for given performance.

Inventors

• 👤 Andrea Ravaglia

Bibliographic Details