EP0177374A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
High-speed semiconductor device
Assignee: Fujitsu Ltd
•
Filing: 1985-07-15
•
Granted: —
•
Expires: 2005-07-15
Abstract
Abstract A high-speed semiconductor device including an emitter layer (18); a base layer (15); a collector layer (13); a potential-barrier layer (14) disposed between the base layer and the collector layer; and a superlattice (16) disposed between the emitter layer and the base layer. The superlattice is formed with at least one quantum well therein and has a low impedance state for tunneling carriers therethrough. Preferably, the high-speed semiconductor device may further include a graded layer (17) disposed between the emitter layer and the superlattice. The graded layer has a conduction-energy level which is approximately equal to that of the emitter layer at one end and is approximatelv equal to a predetermined conduction-energy level of the superlattice at another end. In addition, the high-speed semiconductor device may act as a frequency multiplier.
Inventors
- 👤 Naoki Yokoyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 18:43
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/36; H10D48/362; H10D62/00; H10D62/80; H10D62/81; H10D62/815; H10D62/8161; H10D62/8162; H10D62/8164; H10D62/82; H10D62/824
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
66 words
A high-speed semiconductor device comprising: an emitter layer (18); a base layer (15); a collector layer (13); a potential-barrier means (14) disposed between said base layer (15) and said collector layer (13); and a superlattice means (16) disposed between said emitter layer (18) and said base layer (15), formed with at least one quantum well therein and having a low impedance state for tunneling carriers therethrough.
Claim 2
Dependent Claim
66 words
A high-speed semiconductor device comprising: an emitter layer (18); a base layer (15); a collector layer (13); a potential-barrier means (14) disposed between said base layer (15) and said collector layer (13); and a superlattice means (16) disposed between said emitter layer (18) and said base layer (15), formed with at least one quantum well therein and having a low impedance state for tunneling carriers therethrough.
Claim 3
Dependent Claim
54 words
A high-speed semiconductor device according to claim 1, wherein a conduction-energy level of said carriers tunneled through said superlattice means and injected into said base layer is a predetermined level which is higher than a conduction-band discontinuity (φ c ) at said potential-barrier means (14) and lower than a level subject to intervalley scattering.
Claim 4
Dependent Claim
56 words
A high-speed semiconductor device according to claim 1, wherein said superlattice means (16) includes at least one set of quantum-well forming layer means having thin potential barrier layers (16Al and 16A2) and a thin quantum-well layer (16B) therebetween, which layers are formed with a heterojunction structure and define said quantum well and said low impedance state.
Claim 5
Dependent Claim
34 words
A high-speed semiconductor device according to claim 3, wherein thicknesses of said thin potential barrier layers (16Al and 16A2) and said thin layer (16B) 0 are approximately 3 ~ 50m (30 ~ 50 A).
Claim 6
Dependent Claim
44 words
A high-speed semiconductor device according to claim 3, wherein said superlattice means (16) includes a plurality of sets of said quantum-well forming layer means which are stack-formed with a periodical structure and have at least one conduction mini-energy band for tunneling said carriers therethrough.
Claim 7
Dependent Claim
130 words
A high-speed semiconductor device according to claim 3, wherein said high-speed semiconductor device is formed with any combination of the following materials: (a) said emitter layer (18) GaAs , In x Ga 1-x As (0≦x≦1), (In x As 1-x )m(GaAS)n (1≦m≲3, 1≦n≲3) (b) said superlattice means (16, 16') (bl) barrier layer (16A) (Al x Ga 1-x )As, InP, (In x Al 1-x )As, Al 2 O 3 (b2) quantum well layer (16B) GaAs, (In x Ga 1-x )As (c) said base layer (15) GaAs, (In x Ga 1-x )As, (In x As 1-x )m(GaAs)n, Al (d) said potential barrier means (14) (Al x Ga 1-x )As, I nP, (In x Al 1-x )As (e) said collector layer 13 GaAs, (In x Ga 1-x ) As, (InAS) m (GaAs) n .
Claim 8
Dependent Claim
103 words
A high-speed semiconductor device according to claim 1, further including a graded layer (17) disposed between said emitter layer (18) and said superlattice means (16) and having a conduction-energy level which is approximately equal to that of said emitter layer (18) at one end and is approximately equal to a predetermined conduction-energy level of said superlattice means (16) at another end, to enable tunneling of said carriers therethrough, said carriers in said emitter layer being transported along said graded conduction-energy level in said graded layer (17), tunneled through said superlattice means with said predetermined conduction-energy level, and injected into said base layer (15).
Claim 9
Dependent Claim
33 words
A high-speed semiconductor device according to claim 7, wherein said graded layer is formed with a non-doped impurity Al x Ga l-x As (X:0.3 ~ 0.1) and approximately 10 nm (100 Å) thickness.
Claim 10
Dependent Claim
64 words
A high-speed semiconductor device according to claim 1, wherein a predetermined DC bias is applied to result in a resonant tunneling phenomenon of said carriers at said superlattice means (16) and a signal is output having a 2 to the "n" power multiplied frequency when an input pulse signal having a predetermined voltage range and predetermined slopes is supplied to said base layer (15).
Claim 11
Dependent Claim
30 words
A high-speed semiconductor device according to claim 9, wherein said number "n" is defined by the number of sets of said quantum-well forming layer means in said superlattice means (16).
Claim 12
Dependent Claim
36 words
A high-speed semiconductor device according to claim 1; wherein said emitter layer (18), said superlattice means (16), said base layer (15), said potential-barrier means (14), and said collector layer (13) are formed with a heterojunction structure.
Claim 13
Dependent Claim
19 words
A high-speed semiconductor device according to claim 7, wherein said graded layer (17) is formed with a heterojunction structure.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.