Multiprocessor shared pipeline cache memory

Claim 2

A data processing system comprising: a plurality of data requesting sources, each operative to generate memory requests for data, each request including an address; and, a pipelined cache memory unit coupled to said data requesting sources for receiving said memory requests, said unit including: timing and control means coupled to each of said sources for synchronizing their operations with said cache unit, said timing and control means generating sequences of signals each sequence defining a number of time intervals, at least a different one of said intervals being allocated to each of a number of said sources; a first pipeline' cache stage coupled to said timing and control means, said pipeline stage being conditioned by said timing and control means during one of said time slot intervals in response to said request address being received from one of said sources during one of said allocated time intervals, generating information signals for accessing said requested data when stored in cache; and, a second pipeline cache stage coupled to said timing and control means and to said first pipeline stage, said second pipeline stage being conditioned by said timing means during another one of said time intervals to receive said information signals and access the designated data for transfer to the requesting source enabling the conflict-free processing of requests from said plurality of data requesting sources.

Claim 3

The system of claim 1 wherein said cache memory unit further includes: address selection means coupled to each of said sources for receiving said addresses of said requests, and wherein said timing and control means includes: address select logic means coupled to said plurality of data processing sources and to said address section means, said address select logic means being operative in response to cache request signals received from said sources to generate selection signals for conditioning said address selection means to transfer to said first pipeline cache stage, said request address received from said one of said sources during said one of said allocated time intervals.

Claim 4

The system of claim 2 wherein said timing and control means further includes: master timing means being operative to generate said sequences of signals repetitively, each defining said number of time intervals ; and, start pipeline clocking means coupled to said master timing means and to each of said sources, said start pipeline clocking means including: a plurality of cycle generating means, each coupled to a different one of said sources and to said master timing means, and pipeline timing means coupled to said plurality of cycle generating means and to each of said pipeline stages, said cycle generating means being operative to generate start pipeline signals during said allocated time intervals in response to cache requests defining the types of service required by said plurality of data processing sources; and, said pipeline timing being operative in response to each start pipeline signal to generate a predetermined sequence of pipeline phase signals offset from one of said sequences of signals, different ones of said pipeline phase signals conditioning each of said pipeline stages to carry out those operations required to complete the processing of a cache request during a cache cycle of operation.

Claim 5

The system of claim 3 wherein said system further includes a system bus, a main memory and a plurality of data processing devices connected in common to said system bus, said plurality of data processing sources including a number of central processing unit subsystems and a FIFO subsystem, said FIFO subsystem being coupled to said system bus, each subsystem being coupled to at least one different one of said plurality of cycle generating means, each of said central processing unit subsystems being operative during each of said allocated time intervals to condition a corresponding one of said cycle generating means to initiate a read cycle of operation to fetch data from said cache memory unit and said FIFO subsystem being operative during unused allocated time intervals to condition different ones of said cycle generating means to initiate cache cycles to process replacement and update data received from said system bus.

Claim 6

The system of claim 1 wherein said first pipeline stage of said first and second pipeline stages includes: directory memory means coupled to said timing and control means, said directory memory means having a plurality of locations for storing directory addresses specifying wherein said cache memory unit data is stored and means for generating hit signals indicating whether or not the requested data is stored in said second stage; and, first level command decode means coupled to said directory memory means, to said timing and control means and each of said data processing sources, said first level command decode means being conditioned during said -one of said allocated time intervals to generate control signals for causing said directory memory means to read out said information signals and generate said hit signals for accessing said requested data from said second stage.

Claim 7

The system of claim 5 wherein said second pipeline stage includes: buffer memory means having a plurality of storage locations defined by corresponding ones of said directory addresses; output data register means coupled to said buffer memory means, said timing and control means and to each of said data processing sources; and, second level command decode means coupled to said buffer means, to said timing and control means, and to said first level command decode means, said second level command decode means being conditioned during said another of said time slot intervals to generate control signals for causing said buffer memory means to accept said information signals and access said requested data to be stored in said output data register means for said transfer to one of said sources.

Claim 8

The system of claim 1 wherein said number of said plurality of said data processing sources each includes: clocking means coupled to said timing and control means for receiving timing signals which synchronize the operation of said clocking means with said cache memory unit; and, microprogrammed control means coupled to said clocking means and to said timing and control means, said microprogrammed control means storing and providing microinstructions during firmware cycles of operation, a predetermined field of said microinstructions being coded to specify when said cache request is to be made by a corresponding one of said number of data processing sources during each of said allocated time intervals.

Claim 9

The system of claim 7 wherein said predetermined fields of only predetermined ones of said microinstructions of said microprogrammed control means of each of said number of said data processing sources are coded to specify that a cache request is to be made during cycles defined by those said time intervals allocated to said each of said number of data processing sources.

Claim 10

The system of claim 8 wherein said clocking means of each of said number of said data processing sources conditions said microprogrammed control means to provide said microinstructions during allocated time intervals which are offset from those of another one of said number of said data processing sources by a predetermined number of time intervals for enabling concurrent processing of requests from said number of said data processing sources.

Claim 11

A data processing system comprising: a plurality of data processing subsystems, each being operative to generate memory requests for data, each request including an address; a pipelined cache memory subsystem coupled to each of said data processing subsystems for receiving said data requests, said cache subsystem comprising: timing and control means coupled to each of said data processing subsystems for synchronizing the operations of all of said data processing subsystems with said cache subsystem, said timing and control means generating cycles of clock signals, each defining a corresponding number of time slot intervals, a predetermined number of said time slot intervals being allocated to a corresponding number of said subsystems; input selection means for selecting a request address from one of said subsystems during a corresponding allocated one of said time slots; a first pipeline cache stage coupled to said timing and control means, said pipeline stage being conditioned by said timing and control means during allocated ones of said time slot intervals utilized by corresponding ones of said number of said subsystems to generate address signals in response to said data request received from one of said subsystems specifying where the requested data is stored; and, a second cache pipeline stage coupled to said timing and control means, to said number of said subsystems and to said first pipeline cache stage for receiving said address signals, said second cache pipeline stage being conditioned during a succeeding time slot interval to store said address signals and access the specified data for transfer to a corresponding one of said number of subsystems.

Claim 12

A data processing system comprising: a plurality of data processing subsystems, each being operative to generate memory requests for data, each request including an address; a pipelined cache memory subsystem coupled to each of said data processing subsystems for receiving said data requests, said cache subsystem comprising: timing and control means coupled to each of said data processing subsystems for synchronizing the operations of all of said data processing subsystems with said cache subsystem, said timing and control means generating cycles of clock signals, each defining a corresponding number of time slot intervals, a predetermined number of said time slot intervals being allocated to a corresponding number of said subsystems; input selection means for selecting a request address from one of said subsystems during a corresponding allocated one of said time slots; a first pipeline cache stage coupled to said timing and control means, said pipeline stage being conditioned by said timing and control means during allocated ones of said time slot intervals utilized by corresponding ones of said number of said subsystems to generate address signals in response to said data request received from one of said subsystems specifying where the requested data is stored; and, a second cache pipeline stage coupled to said timing and control means, to said number of said subsystems and to said first pipeline cache stage for receiving said address signals, said second cache pipeline stage being conditioned during a succeeding time slot interval to store said address signals and access the specified data for transfer to a corresponding one of said number of subsystems.