Semiconductor circuit

Claim 2

A semiconductor circuit comprising: at least one input-change detecting circuit having a first output end for generating a pulse in response to a change of an input signal; a gate circuit, having an input end operatively connected to said first output end and having a second output end, for changing the signal at said second output end when said input signal changes; and a pulse-width fixing circuit for latching the output signal of said gate circuit in response to a signal change at said second output end of said gate circuit and for resetting said latching a predetermined time after the latching.

Claim 3

A semiconductor circuit as set forth in claim 1, wherein said pulse-width fixing circuit comprises: a latch and reset circuit and a control circuit having an input end connected to said second output end of said gate circuit and having an output end connected to said latch and reset circuit, said control circuit including a delay circuit for transferring a signal change at said input end to said output end with a predetermined time delay.

Claim 4

A semiconductor circuit as set forth in claim 2, wherein said latch and reset circuit comprises: latching means for latching a signal change at said second output end and resetting means for resetting said latching after said predetermined time delay from said latching.

Claim 5

A semiconductor circuit as set forth in claim 3, wherein said gate circuit further comprises an inverter having an input end, connected to said second output end, and an output end, said latching means compr ' sing a first transistor having a gate electrode connected to said output end of said inverter and a second transistor having a gate electrode connected to said output end of said control circuit, said first and second transistors being connected in series between a power supply and said second output end of said gate circuit.

Claim 6

A semiconductor circuit as set forth in claim 4, wherein said resetting means comprises a third transistor having a gate electrode connected to said output end of said inverter and a fourth transistor having a gate electrode connected to said output end of said control circuit, said third and fourth transistors being connected between said gate circuit and a ground power supply.

Claim 7

A semiconductor circuit as set forth in claim 5, wherein said control circuit comprises: a first inverter having an input end connected to said second output end of said gate circuit; a second inverter having an input end connected to the output end of said first inverter and having an output end connected to the gate electrodes of said second transistor and said fourth transistor; a resistor connected between said first inverter and the ground power supply; and a capacitor connected between the output end of said first inverter and the ground power supply; said resistor and said capacitor forming said delay circuit.

Claim 8

A semiconductor circuit as set forth in any one of claims 1 to 6, wherein said input-change detecting circuit operatively receives an address signal for accessing a memory device.

Claim 9

A semiconductor circuit as set forth in any one of claims 1 to 6, wherein said input-change detecting circuit operatively receives a chip select signal for selecting a memory chip of a memory device.

Claim 10

A semiconductor circuit as set forth in any one of claims 1 to 6, wherein said input-change detecting circuit operatively receives a write enable signal for enabling a write operation of a memory device.

Claim 11

A semiconductor circuit as set forth in any one of claims 1 to 9, wherein said pulse-width fixing circuit generates a pulse having a constant pulse width.

Claim 12

A semiconductor circuit as set forth in claim 10, wherein said pulse is used as a clock signal for short-circuiting pairs of bit lines in a memory device.