EP0176218A2
Expired / Lapsed
EP
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Error correcting system
Assignee: NEC Corp
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Filing: 1985-08-19
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Granted: —
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Expires: 2005-08-19
Abstract
Abstract Data (X) to be transmitted to an external device, such as a memory (5), is applied to an error correction code generator (2) and a parity generator (3) to generate an error correction code (C) and parity bit (p) to accompany the data. The received data (X.) is applied to an error correction code generator (7) and a parity generator (8) to generate a second error correction code (C b ) and a second parity bit (P b ). The second error correction code (C b ) is compared with the received error correction code (C.) in a comparison circuit (9) which generates an error correction code (S) when there is a discrepancy. The second parity bit (P b ) is compared with the received parity bit (P.) and a signal (m) is generated when the bits are different. An enabling circuit (11) provides an enabling signal (n) only when the correction code (S) and the parity mis-match signal (m) are both present. The enabling signal (n) enables an error correction circuit (12) to correct the received data (X a ) in accordance with the error correction code (S). Correction does not take place when the enabling signal is absent.
Inventors
- 👤 Hiromu C/O Nec Corporation Masuhara
- 👤 Tsunekazu C/O Nec Corporation Kimura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-31 23:47
CPC Classifications
H; H03; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/13; H03M13/19; G; G11; G11B; G11B20/00; G11B20/10; G11B20/18; G11B20/1833
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
328 words
An error correcting system comprising a first error correcting code generator (2) for generating a first error correcting code (C) to be added to data (X) to be transmitted; a first parity bit generator (3) for generating a first parity bit (p) associated with the data; transmitting means (4) for transmitting the data accompanied by the first error correcting code and the first parity bit to an external circuit (5); receiving means (6) for receiving data (X a ) accompanied by a received first error correcting code (C a ) and a received first parity bit ( Pa ) corresponding to the transmitted data, first error correcting code and first parity bit, from the external circuit (5); a second error correcting code generator (7) for generating a second error correcting code (C b ) to be added to the received data; a second parity bit generator (8) for generating a second parity bit ( Pb ) associated with the received data; an error correction signal generator (9) for comparing the received first error correcting code (C a ) and the second error correcting code (C b ) and generating an error correction signal ( S ) when a difference between these codes is found; a parity check means (10) for comparing the received first parity bit ( Pa ) and the second parity bit ( Pb ) and outputting a parity error signal (m) when the first and second parity bits are different; an error correction enabling circuit (11) for outputting an error correction enabling signal (n) when the error correction signal (S) and the parity error signal (m) are generated; and an error correction circuit (12) for correcting the error of the received data (X a ) in accordance with the error correction signal (S) when the error correction enabling signal (n) is present, the error correction circuit (12) outputting the received data (X a ) without error correction when the error correction enabling signal is absent.
Claim 2
Dependent Claim
328 words
An error correcting system comprising a first error correcting code generator (2) for generating a first error correcting code (C) to be added to data (X) to be transmitted; a first parity bit generator (3) for generating a first parity bit (p) associated with the data; transmitting means (4) for transmitting the data accompanied by the first error correcting code and the first parity bit to an external circuit (5); receiving means (6) for receiving data (X a ) accompanied by a received first error correcting code (C a ) and a received first parity bit ( Pa ) corresponding to the transmitted data, first error correcting code and first parity bit, from the external circuit (5); a second error correcting code generator (7) for generating a second error correcting code (C b ) to be added to the received data; a second parity bit generator (8) for generating a second parity bit ( Pb ) associated with the received data; an error correction signal generator (9) for comparing the received first error correcting code (C a ) and the second error correcting code (C b ) and generating an error correction signal ( S ) when a difference between these codes is found; a parity check means (10) for comparing the received first parity bit ( Pa ) and the second parity bit ( Pb ) and outputting a parity error signal (m) when the first and second parity bits are different; an error correction enabling circuit (11) for outputting an error correction enabling signal (n) when the error correction signal (S) and the parity error signal (m) are generated; and an error correction circuit (12) for correcting the error of the received data (X a ) in accordance with the error correction signal (S) when the error correction enabling signal (n) is present, the error correction circuit (12) outputting the received data (X a ) without error correction when the error correction enabling signal is absent.
Claim 3
Dependent Claim
63 words
An error correcting system according to claim 1, characterised in that the external circuit includes a memory (5) for storing the data to be transmitted, together with the first error correcting code and first parity bit, the transmitting means includes an output buffer circuit (4) coupled to the memory and the receiving means includes an input buffer circuit (6) coupled to the memory.
Claim 4
Dependent Claim
38 words
An error correcting system according to claim 1 or 2, characterised in that the first and second error correcting code generators (2 and 7) are provided by a single error correcting code generator used in time shared manner.
Claim 5
Dependent Claim
32 words
An error correcting system according to claim 3, characterised in that the error correcting code generator (2, 7) includes a circuit for generating check bits based on the error correcting code technique.
Claim 6
Dependent Claim
38 words
An error correcting system according to any of claims 1 to 4, characterised in that the first and second parity bit generators (3, 8) are provided by a single parity bit generator used in the time shared manner.
Claim 7
Dependent Claim
246 words
An error correction apparatus comprising receiving means (6) for receiving digital data (X a ), accompanied by a first error correcting code (C a ) added to the digital data for correction of bit errors thereof, and a first parity bit ( Pa ) associated with the digital data, an error correcting code generator (7) for generating a second error correcting code (C b ) based on the received digital data (X a ), a parity bit generator (8) for generating a second parity bit ( Pb ) based on the received digital data (X a), means (9) for comparing the received first error correcting code (C a ) and the generated second error correcting code (C b ) and generating an error correction signal (S) when these codes are different, means (10) for comparing the received first parity bit ( Pa ) and the generated second parity bit ( Pb ) and generating a parity error signal (m) when a difference is detected between these bits, means (11) for generating an enabling signal (n) in response to generation of the error correction signal (S) and the parity error signal (m), and an error correction circuit (12) for correcting an error in the received digital data (X ) by use of the error correction signal (S) only when the enabling signal (n) is generated, the error correction circuit (12) outputting the received digital data (X a ) as it is when the enabling signal is absent.
Claim 8
Dependent Claim
246 words
An error correction apparatus comprising receiving means (6) for receiving digital data (X a ), accompanied by a first error correcting code (C a ) added to the digital data for correction of bit errors thereof, and a first parity bit ( Pa ) associated with the digital data, an error correcting code generator (7) for generating a second error correcting code (C b ) based on the received digital data (X a ), a parity bit generator (8) for generating a second parity bit ( Pb ) based on the received digital data (X a), means (9) for comparing the received first error correcting code (C a ) and the generated second error correcting code (C b ) and generating an error correction signal (S) when these codes are different, means (10) for comparing the received first parity bit ( Pa ) and the generated second parity bit ( Pb ) and generating a parity error signal (m) when a difference is detected between these bits, means (11) for generating an enabling signal (n) in response to generation of the error correction signal (S) and the parity error signal (m), and an error correction circuit (12) for correcting an error in the received digital data (X ) by use of the error correction signal (S) only when the enabling signal (n) is generated, the error correction circuit (12) outputting the received digital data (X a ) as it is when the enabling signal is absent.
References Cited (Backward Citations)
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