Integrated circuit fabrication process and device

Claim 2

A process for fabricating integrated , circuits, comprising the steps of: providing a substrate having semiconductor active device regions near the surface thereof; providing an insulating layer above predetermined portions of said active device regions; defining a first metal interconnect layer which interconnects predetermined portions of said active device regions to configure a predetermined circuit function; providing an interlevel dielectric above said first metal interconnect layer, and anisotropically etching said interlevel dielectric to expose said first metal interconnect layer at predetermined via locations; conformally depositing an additional layer of insulating material, and anisotropically etching said additional layer of insulating material to remove it from exposed flat surfaces, whereby said exposed via locations are narrowed at the periphery thereof by remaining portions of said additional layer of insulating material; and depositing and patterning an additional layer of conductive material, to interconnect said via areas in a predetermined pattern.

Claim 3

A process for fabricating integrated circuits, comprising the steps of: providing a substrate having semiconductor active device regions near the surface thereof, said device regions comprising field-effect transistors comprising gates defined in a layer of polycrystalline material comprising silicon; providing an interlevel dielectric above said gate layer, and anisotropically etching said interlevel dielectric to expose said gate layer at predetermined via locations; conformally depositing an additional layer of insulating material, and anisotropically etching said additional layer of insulating material to remove it from exposed flat surfaces, whereby said exposed via locations are narrowed at the periphery thereof by remaining portions of said additional layer of insulating material; and depositing and patterning an additional layer of conductive material, to interconnect said via areas in a predetermined pattern.

Claim 4

A process for fabricating integrated circuits, comprising the steps of: providing a substrate having semiconductor active device regions near the surface thereof, said device regions comprising field-effect transistors comprising gates defined in a layer of polycrystalline material comprising silicon; providing an interlevel dielectric above said gate layer, and anisotropically etching said interlevel dielectric to expose said gate layer at predetermined via locations; conformally depositing an additional layer of insulating material, and anisotropically etching said additional layer of insulating material to remove it from exposed flat surfaces, whereby said exposed via locations are narrowed at the periphery thereof by remaining portions of said additional layer of insulating material; and depositing and patterning an additional layer of conductive material, to interconnect said via areas in a predetermined pattern.

Claim 5

A process for fabricating integrated circuits, comprising the steps of: providing a substrate having semiconductor active device regions near the surface thereof, said device regions comprising field-effect transistors comprising gates defined in a layer of polycrystalline material comprising silicon; providing a first interlevel dielectric above said gate layer, patterning said first interlevel dielectric to expose predetermined contact locations in said gate layer and also predetermined contact locations in said active device regions, and defining a first metal interconnect layer which interconnects predetermined portions of said active device regions and of said gate layer to at least partially configure a predetermined circuit function; providing a second interlevel dielectric above said first metal interconnect layer, and anisotropically etching said second interlevel dielectric to expose said first metal interconnect layer at predetermined second via locations and also to expose said gate layer at other predetermined second via locations; conformally depositing an additional layer of insulating material, and anisotropically etching said additional layer of insulating material to remove it from exposed flat surfaces, whereby said exposed second via locations are narrowed at the periphery thereof by remaining portions of said additional layer of insulating material; and depositing and patterning an additional layer of conductive material, to interconnect said second via locations in a predetermined pattern.

Claim 6

A process for fabricating integrated circuits, comprising the steps of: providing a substrate having semiconductor active device regions near the surface thereof, said device regions comprising field-effect transistors comprising gates defined in a layer of polycrystalline material comprising silicon; providing a first interlevel dielectric above said gate layer, patterning said first interlevel dielectric to expose predetermined contact locations in said gate layer and also predetermined contact locations in said active device regions, and defining a first metal interconnect layer which interconnects predetermined portions of said active device regions and of said gate layer to at least partially configure a predetermined circuit function; providing a second interlevel dielectric above said first metal interconnect layer, and anisotropically etching said second interlevel dielectric to expose said first metal interconnect layer at predetermined second via locations and also to expose said gate layer at other predetermined second via locations; conformally depositing an additional layer of insulating material, and anisotropically etching said additional layer of insulating material to remove it from exposed flat surfaces, whereby said exposed second via locations are narrowed at the periphery thereof by remaining portions of said additional layer of insulating material; and depositing and patterning an additional layer of conductive material, to interconnect said second via locations in a predetermined pattern.

Claim 7

A process for fabricating integrated circuits, comprising the steps of: providing a substrate having semiconductor active device regions near the surface thereof; providing an insulating layer above predetermined contact locations of said active device regions and also above other portions of said active device regions; anisotropically etching said insulating layer to expose a plurality of said contact areas; conformally depositing an additional layer of insulating material, and anisotropically etching said additional layer of insulating material to remove it from exposed flat surfaces, whereby said exposed contact areas are narrowed at the periphery thereof by remaining portions of said additional layer of insulating material; and depositing and patterning a layer of conductive material, to interconnect said contact areas in a predetermined pattern.

Claim 8

A process for fabricating integrated circuits, comprising the steps of: providing a substrate having semiconductor active device regions near the surface thereof; providing an insulating layer above predetermined contact locations of said active device regions and also above other portions of said active device regions; anisotropically etching said insulating layer to expose a plurality of said contact areas; conformally depositing an additional layer of insulating material, and anisotropically etching said additional layer of insulating material to remove it from exposed flat surfaces, whereby said exposed contact areas are narrowed at the periphery thereof by remaining portions of said additional layer of insulating material; and depositing and patterning a layer of conductive material, to interconnect said contact areas in a predetermined pattern.

Claim 9

A process for fabricating integrated circuits, comprising the steps of: providing a substrate having semiconductor active device regions near the surface thereof, said device regions comprising field-effect transistors comprising gates defined in a layer of polycrystalline material comprising silicon; providing an interlevel dielectric above said gate layer, and anisotropically etching said interlevel dielectric to expose said gate layer at predetermined via locations, and also expose said active device regions at predetermined contact locations; conformally depositing an additional layer of insulating material, and anisotropically etching said additional layer of insulating material to remove it from exposed flat surfaces, whereby said exposed contact and via locations are narrowed at the periphery thereof by remaining portions of said additional layer of insulating material; and depositing and patterning an additional layer of conductive material, to interconnect said contact and via areas in a predetermined pattern.

Claim 10

A process for fabricating integrated circuits, comprising the steps of: providing a substrate having semiconductor active device regions near the surface thereof, said device regions comprising field-effect transistors comprising gates defined in a layer of polycrystalline material comprising silicon; providing an interlevel dielectric above said gate layer, and anisotropically etching said interlevel dielectric to expose said gate layer at predetermined via locations, and also expose said active device regions at predetermined contact locations; conformally depositing an additional layer of insulating material, and anisotropically etching said additional layer of insulating material to remove it from exposed flat surfaces, whereby said exposed contact and via locations are narrowed at the periphery thereof by remaining portions of said additional layer of insulating material; and depositing and patterning an additional layer of conductive material, to interconnect said contact and via areas in a predetermined pattern.

Claim 11

The process of Claim 1, wherein said step of depositing and additional layer of insulating material comprises low pressure chemical vapor deposition of silicon oxides.

Claim 12

The process of Claim 1, wherein said step of depositing and additional layer of insulating material comprises low temperature plasma-assisted deposition of silicon oxides.

Claim 13

The process of Claim 2, wherein said gate layer comprises polycrystalline silicon.

Claim 14

The process of Claim 2, wherein said gate layer comprises a metal silicide compound.

Claim 15

An integrated circuit comprising: a substrate; a plurality of semiconductor active device regions close to the surface of said substrate; a patterned insulating layer overlying said active device regions, said patterned insulator layer being patterned to expose contact locations; at least one patterned conductive layer above said insulating layer, said patterned conductive layer making contact to said active device regions at predetermined ones of said contact areas; wherein said patterned conductive layer is not substantially wider above said contact areas where said conductive layer makes contact than over said portions of said insulating layer where said conductive layer does not make contact to said active device regions.

Claim 16

An integrated circuit comprising: a substrate; a plurality of semiconductor active device regions close to the surface of said substrate; a patterned insulating layer overlying said active device regions, said patterned insulator layer being patterned to expose contact locations; at least one patterned conductive layer above said insulating layer, said patterned conductive layer making contact to said active device regions at predetermined ones of said contact areas; wherein said patterned conductive layer is not substantially wider above said contact areas where said conductive layer makes contact than over said portions of said insulating layer where said conductive layer does not make contact to said active device regions.

Claim 17

An integrated circuit comprising: a substrate; a plurality of semiconductor active device regions close to the surface of said substrate, said device regions comprising field-effect transistors comprising gates defined in a gate interconnect layer comprising polycrystalline conductive material; a first interlevel dielectric layer overlying said active device regions and said gate interconnect layer, said first interlevel dielectric layer being patterned to expose contact locations; a first patterned metal layer above said insulating layer, said first metal layer making electrical contact at ones of said contact locations; a second interlevel dielectric above said first metal layer which exposes said first metal layer at predetermined second via locations; a second metal layer overlying said second interlevel dielectric and making contact to said dfirst metal layer at said second via locations; wherein said second metal layer is not substantially wider above said second via locations than over said portions of said second interlevel dielectric where said second metal layer does not make contact to said first metal layer.

Claim 18

An integrated circuit comprising: a substrate; a plurality of semiconductor active device regions close to the surface of said substrate, said device regions comprising field-effect transistors comprising gates defined in a gate interconnect layer comprising polycrystalline conductive material; a first interlevel dielectric layer overlying said active device regions and said gate interconnect layer, said first interlevel dielectric layer being patterned to expose contact locations; a first patterned metal layer above said insulating layer, said first metal layer making electrical contact at ones of said contact locations; a second interlevel dielectric above said first metal layer which exposes said first metal layer at predetermined second via locations; a second metal layer overlying said second interlevel dielectric and making contact to said dfirst metal layer at said second via locations; wherein said second metal layer is not substantially wider above said second via locations than over said portions of said second interlevel dielectric where said second metal layer does not make contact to said first metal layer.

Claim 19

An integrated circuit comprising: a substrate; a plurality of semiconductor active device regions close to the surface of said substrate, said device regions comprising field-effect transistors comprising gates defined in a gate interconnect layer comprising polycrystalline conductive material; a first interlevel dielectric layer overlying said active device regions and said gate interconnect layer, said first interlevel dielectric layer being patterned to expose contact locations; a first patterned metal layer above said insulating layer, said first metal layer making electrical contact at ones of said contact locations; a second interlevel dielectric above said first metal layer which exposes said first metal layer at predetermined second via locations; a second metal layer overlying said second interlevel dielectric and making contact to said dfirst metal layer at said second via locations; wherein said first metal layer is not substantially wider at said second via locations than under portions of said second interlevel dielectric where said second metal layer does not make contact to said first metal layer.

Claim 20

An integrated circuit comprising: a substrate; a plurality of semiconductor active device regions close to the surface of said substrate, said device regions comprising field-effect transistors comprising gates defined in a gate interconnect layer comprising polycrystalline conductive material; a first interlevel dielectric layer overlying said active device regions and said gate interconnect layer, said first interlevel dielectric layer being patterned to expose contact locations; a first patterned metal layer above said insulating layer, said first metal layer making electrical contact at ones of said contact locations; a second interlevel dielectric above said first metal layer which exposes said first metal layer at predetermined second via locations; a second metal layer overlying said second interlevel dielectric and making contact to said dfirst metal layer at said second via locations; wherein said first metal layer is not substantially wider at said second via locations than under portions of said second interlevel dielectric where said second metal layer does not make contact to said first metal layer.

Claim 21

An integrated circuit comprising: a substrate; a plurality of semiconductor active device regions close to the surface of said substrate, said device regions comprising field-effect transistors comprising gates defined in a gate interconnect layer comprising polycrystalline conductive material; a first interlevel dielectric layer overlying said active device regions and said gate interconnect layer, said first interlevel dielectric layer being patterned to expose contact locations in said gate interconnect layer; a first patterned metal layer above said first interlevel dielectric layer, said first metal layer making electrical contact to said gate interconnect layer at ones of said contact locations; wherein said first metal layer is not substantially wider at said contact locations than over portions of said first interlevel dielectric where said first metal layer does not make contact to said gate interconnect layer.

Claim 22

An integrated circuit comprising: a substrate; a plurality of semiconductor active device regions close to the surface of said substrate, said device regions comprising field-effect transistors comprising gates defined in a gate interconnect layer comprising polycrystalline conductive material; a first interlevel dielectric layer overlying said active device regions and said gate interconnect layer, said first interlevel dielectric layer being patterned to expose contact locations in said gate interconnect layer; a first patterned metal layer above said first interlevel dielectric layer, said first metal layer making electrical contact to said gate interconnect layer at ones of said contact locations; wherein said first metal layer is not substantially wider at said contact locations than over portions of said first interlevel dielectric where said first metal layer does not make contact to said gate interconnect layer.

Claim 23

An integrated circuit comprising: a substrate; a plurality of semiconductor active device regions close to the surface of said substrate, said device regions comprising field-effect transistors comprising gates defined in a gate interconnect layer comprising polycrystalline conductive material; a first interlevel dielectric layer overlying said active device regions and said gate interconnect layer, said first interlevel dielectric layer being patterned to expose contact locations in said gate interconnect layer; a first patterned metal layer above said first interlevel dielectric layer, said first metal layer making electrical contact to said gate interconnect layer at ones of said contact locations; wherein said gate interconnect layer is not substantially wider at said contact locations than under portions of said first interlevel dielectric where said metal layer does not make contact to said gate interconnect layer.

Claim 24

An integrated circuit comprising: a substrate; a plurality of semiconductor active device regions close to the surface of said substrate, said device regions comprising field-effect transistors comprising gates defined in a gate interconnect layer comprising polycrystalline conductive material; a first interlevel dielectric layer overlying said active device regions and said gate interconnect layer, said first interlevel dielectric layer being patterned to expose contact locations in said gate interconnect layer; a first patterned metal layer above said first interlevel dielectric layer, said first metal layer making electrical contact to said gate interconnect layer at ones of said contact locations; wherein said gate interconnect layer is not substantially wider at said contact locations than under portions of said first interlevel dielectric where said metal layer does not make contact to said gate interconnect layer.