Integrated circuit for arithmetic operation and display

Claim 2

An integrated circuit for arithmetic operation and display control connected to a power source (46) and a liquid crystal display device (45), and energized by the power source, said integrated circuit including an arithmetic operation circuit (42) for performing a designated arithmetic operation, wherein the result of the arithmetic operation is displayed by the display device, said integrated circuit further comprising: a boosting circuit (43) receiving and boosting the voltage from said power source (46), a drive circuit (44) powered by said boosting circuit (43) and driving said liquid crystal display device (45), and a control circuit (41) causing interruption of the driving of the display device when the arithmetic operation circuit (42) is carrying out the arithmetic operation.

Claim 3

A circuit of claim 1, wherein said control circuit produces a control signal to cause interruption of the operation of the drive circuit for driving the display device and/or the operation of the boosting circuit for boosting, when the arithmetic operation circuit carries out the arithmetic operation.

Claim 4

A circuit of claim 1, wherein said boosting circuit comprises: a first capacitor (114) accumulating an electric charge across a first terminal (a) and a second terminal (b), a second capacitor (116) accumulating an electric charge across a third terminal (c) and a fourth terminal (d), with said fourth terminal being connected to a first power source line (V ), - a first and a second MOSFET's (110, 112) respectively connecting the first terminal (a) to the first power source line (V SS ) and the second terminal (b) to a second power source line V , the first and the second MOSFET's forming a first group of MOSFET's, a third and a fourth MOSFET's (111,113) respectively connecting the first terminal (a) to the second power source line (V DD ) and the second terminal (b) to the third terminal (c), the third and the fourth MOSFET's forming a second group of MOSFET's, and a fifth MOSFET (115) connecting the third terminal (c) to the second power source line V , and said control circuit causes, when the arithmetic operation circuit is not carrying out the arithmetic operation, the fifth MOSFET to be OFF and said first group of MOSFET's and said second group of MOSFET's to be ON and OFF alternately to produce a boosted voltage at the third terminal, and causes, when the arithmetic operation circuit is carrying out the arithmetic operation, the fifth MOSFET to be ON to interrupt the boosting operation.

Claim 5

A circuit of claim 3, wherein said control circuit causes, when the arithmetic operation circuit is carrying out the arithmetic operation, the first group of MOSFET's to be ON, and the second group of MOSFET's to be OFF.

Claim 6

A circuit of claim 3, wherein said liquid crystal display device (45) comprises a plurality of liquid crystal segments (45S), segment terminals (208) for the respective liquid crystal display segments, and a common terminal (217), and said control circuit causes, when the arithmetic operation circuit is not carrying out the arithmetic operation, the potential at said segment terminals to periodically change to turn on or turn off the liquid crystal display segments connected between the segment terminals and the common terminal, and causes, when the arithmetic operation circuit is carrying out the arithmetic operation, the potentials at the common terminal and the segment terminals to be maintained identical with each other and at a predetermined value.

Claim 7

A circuit of claim 1, wherein said liquid crystal display device (45) comprises a plurality of liquid crystal segments (45S), segment terminals (208) for the respective liquid crystal display segments, and a common terminal (217), and said control circuit causes, when the arithmetic operation circuit is not carrying out the arithmetic operation, the potential at said segment terminals to periodically change to turn on or turn off the liquid crystal display segments connected between the segment terminals and the common terminal, and causes, when the arithmetic operation circuit is carrying out the arithmetic operation, the potentials at the common terminal and the segment terminals to be maintained identical with each other and at a predetermined value.