MOS dynamic RAM and manufacturing method thereof

Claim 1

A MOS dynamic RAM constructed by integrated memory cells each having a MOSFET and a MOS capacitor comprising: a semiconductor substrate (10, 310, 310a, 410) of a first conductivity type; a drain region (12, 310b, 412) formed on said semiconductor substrate; a channel region (16, 310c, 416) of the first conductivity type formed on said drain region; a source region (18, 118, 118a, 118b, 118c, 318a, 318b) of a second conductivity type formed on said channel region; a gate insulating film (20, 320) formed to be in contact with said channel region between said source and drain regions; and a gate electrode (22, 122, 222a, 222b, 322) formed to be in contact with said gate insulating film, characterized in that: projections (14, 314, 414) and recesses (34, 134, 334) are periodically formed on said semiconductor substrate, said source region (18, 118, 118a, 118b, 118c, 318a, 318b) is formed in an upper surface of each of said projections, said drain region (12, 310b, 412) is formed in a bottom portion of each of said projections, and said gate insulating film (20, 320) and said gate electrode (22, 122, 222a, 222b, 322) are formed in each of said recesses; that a first'insulating film (24, 324) is formed on said source region, a first electrode (26, 26b, 326) of the MOS capacitor is formed on said first insulating film, the MOS capacitor is constituted by said source region, said first insulating film and said first electrode, and said source region serves as a second electrode of the MOS capacitor; and that said gate electrode serves as a word line (WL1, WL2, WL3, WL4), and said first electrode of the MOS capacitor serves as a bit line (BL1, BL2, BL3).

Claim 29

A method of manufacturing a MOS dynamic RAM constructed by integrated memory cells each having a MOSFET and a MOS capacitor, characterized by comprising the steps of: forming a first semiconductor layer (12) of a second conductivity type having a high impurity concentration as a drain region of the MOSFET in a prospective memory cell region of a semiconductor substrate (10); forming a second semiconductor layer (16a) of the second conductivity type having a low impurity concentration on said first semiconductor layer; forming a third semiconductor layer (18a) of a first conductivity type having a high impurity concentration as a source region of the MOSFET on a surface of said second semiconductor layer; selectively etching from a surface of said third semiconductor layer (18a) to the depth of said first semiconductor layer (12) so as to form periodic projections (14) and recesses; forming a gate electrode (22) on the side walls of each of said projections (14) through a gate insulating film; and forming through an insulating film (24) a first electrode of the MOS capacitor on said third semiconductor layer (18) which serves as a second electrode of the MOS capacitor and which remains on a surface of each of said projections.

Claim 30

A method of manufacturing a MOS dynamic RAM constructed by integrated memory cells each having a MOSFET and a MOS capacitor, characterized by comprising the steps of: forming a first semiconductor layer (12) of a second conductivity type having a high impurity concentration as a drain region of the MOSFET in a prospective memory cell region of a semiconductor substrate (10); forming a second semiconductor layer (16a) of the second conductivity type having a low impurity concentration on said first semiconductor layer; forming a third semiconductor layer (18a) of a first conductivity type having a high impurity concentration as a source region of the MOSFET on a surface of said second semiconductor layer; selectively etching from a surface of said third semiconductor layer (18a) to the depth of said first semiconductor layer (12) so as to form periodic projections (14) and recesses; forming a gate electrode (22) on the side walls of each of said projections (14) through a gate insulating film; and forming through an insulating film (24) a first electrode of the MOS capacitor on said third semiconductor layer (18) which serves as a second electrode of the MOS capacitor and which remains on a surface of each of said projections.

Claim 32

A method of manufacturing a MOS dynamic RAM constructed by integrated memory cells each having a MOSFET and a MOS capacitor, characterized by comprising the steps of: forming a first semiconductor layer (310b) of a second conductivity type having a high impurity concentration as a drain region of the MOSFET on a prospective memory cell region of a semiconductor substrate (310a); epitaxially growing a second semiconductor layer (310c) of the second conductivity type having a low impurity concentration on said first semiconductor layer; selectively etching said second semiconductor layer (310c) to said first semiconductor layer (310b) so as to form periodic projections and recesses; forming a gate electrode (322) on side walls of each of said projections through a gate insulating film (320); forming a source region (318a, 318b) of the second conductivity type in second semiconductor layer (310c) which remains on a surface of each of said projections; forming a first electrode (360) of the MOS capacitor for connecting a pair of source regions (318a, 318b) which are opposite to each other across each of said recesses, said first electrode being formed through a first insulating film (362) so as to cover said gate electrode formed in each of said recesses; and forming a second electrode (326) of the MOS capacitor on said first electrode through a second insulating film.

Claim 33

A method of manufacturing a MOS dynamic RAM constructed by integrated memory cells each having a MOSFET and a MOS capacitor, characterized by comprising the steps of: forming a first semiconductor layer (310b) of a second conductivity type having a high impurity concentration as a drain region of the MOSFET on a prospective memory cell region of a semiconductor substrate (310a); epitaxially growing a second semiconductor layer (310c) of the second conductivity type having a low impurity concentration on said first semiconductor layer; selectively etching said second semiconductor layer (310c) to said first semiconductor layer (310b) so as to form periodic projections and recesses; forming a gate electrode (322) on side walls of each of said projections through a gate insulating film (320); forming a source region (318a, 318b) of the second conductivity type in second semiconductor layer (310c) which remains on a surface of each of said projections; forming a first electrode (360) of the MOS capacitor for connecting a pair of source regions (318a, 318b) which are opposite to each other across each of said recesses, said first electrode being formed through a first insulating film (362) so as to cover said gate electrode formed in each of said recesses; and forming a second electrode (326) of the MOS capacitor on said first electrode through a second insulating film.