EP0175102A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Toshiba Corp
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Filing: 1985-07-29
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Granted: —
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Expires: 2005-07-29
Abstract
Abstract A semiconductor memory device provided with first and second bit lines (11, 12), each of which is connected to a memory cell (15) comprising a nonvolatile transistor (13) and a dummy cell (18) comprising a nonvolatile transistor (16). The first and second bit lines (11, 12) are respectively connected to high voltage generators (19" 19,) which are applied at the time of data programming. At the time of data reading, data-detecting and storing means (20) comprising a flip-flop circuit (27) detects data, while amplifying a potential difference between the first and second bit lines. At the time of data writing, the data detecting and storing means (20) temporarily stores data in accordance with the contents of externally supplied writing data. A first switching transistor (32) is provided between the first data input-output node of the data-detecting and storing means and the first bit line. The second switching transistor (34) is connected between the second data input-output node of the data-detecting and storing means and second bit line. The paired switching transistors are controlled in accordance with the operation mode of the memory device.
Inventors
- 👤 Junichi C/O Patent Division Miyamoto
- 👤 Jun-Ichi C/O Patent Division Tsujimoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 16:00
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/26; G11C16/28
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
181 words
A semiconductor memory device characterized by comprising: a first bit line (11) connected to memory cells (15) each comprising a nonvolatile transistor (13) and a dummy cell (18) comprising a nonvolatile transistor; a second bit line (12) connected to memory cells (15) each comprising a nonvolatile transistor (13) and a dummy cell (18) comprising a nonvolatile transistor; first and second high voltage generators (19 1 , 19 2 ) respectively connected to said first and second bit lines; data-detecting and storing means (20) which comprises a flip-flop circuit (27) provided with first and second input-output nodes (31, 33) and, at the time of data reading, detects data while amplifying a potential difference between the first and second bit lines, and, at the time of data writing, temporarily stores data corresponding to the externally supplied writing data; a switching transistor (32) provided between the first data input-output node of said data-detecting and storing means and said first bit line; and a switching transistor (34) provided between the second data input-output node of said data-detecting and storing means and said second bit line.
Claim 2
Dependent Claim
181 words
A semiconductor memory device characterized by comprising: a first bit line (11) connected to memory cells (15) each comprising a nonvolatile transistor (13) and a dummy cell (18) comprising a nonvolatile transistor; a second bit line (12) connected to memory cells (15) each comprising a nonvolatile transistor (13) and a dummy cell (18) comprising a nonvolatile transistor; first and second high voltage generators (19 1 , 19 2 ) respectively connected to said first and second bit lines; data-detecting and storing means (20) which comprises a flip-flop circuit (27) provided with first and second input-output nodes (31, 33) and, at the time of data reading, detects data while amplifying a potential difference between the first and second bit lines, and, at the time of data writing, temporarily stores data corresponding to the externally supplied writing data; a switching transistor (32) provided between the first data input-output node of said data-detecting and storing means and said first bit line; and a switching transistor (34) provided between the second data input-output node of said data-detecting and storing means and said second bit line.
Claim 3
Dependent Claim
34 words
The semiconductor memory device according to claim 1, characterized in that, at the time of data writing, said data-detecting and storing means (20) is supplied with data inverted from said externally supplied writing data.
Claim 4
Dependent Claim
41 words
The semiconductor memory device according to claim 1, characterized in that said first and second switching transistors (32, 34) are rendered conductive at the time of data reading or data programming, and are rendered nonconductive at the time of data erasing.
Claim 5
Dependent Claim
35 words
The semiconductor memory device according to claim 1, characterized in that said data-detecting and storing means (20) is provided in common to a plurality of first bit lines and a plurality of second bit lines.
Claim 6
Dependent Claim
31 words
The semiconductor memory device according to claim 1, characterized in that said memory cell (15) comprises a data-storing nonvolatile transistor (13) and a selection transistor (14) for specifying said nonvolatile transistor.
Claim 7
Dependent Claim
230 words
A semiconductor memory device characterized by comprising: a first bit line (11) connected to memory cells (15) each comprising a nonvolatile transistor (13) and a dummy cell (18) comprising a nonvolatile transistor (16); a second bit line (12) connected to memory cells (15) each comprising a nonvolatile transistor (13) and a dummy cell (18) comprising a nonvolatile transistor (16); first and second high voltage generating means (19 1 , 19 2 ) respectively connected to said first and second bit lines; data-detecting and storing means (20) comprising a flip-flop circuit (27) provided with first and second data input-output nodes (31, 33); a first switching transistor (32) connected between the first data input-output node of said data-detecting and storing means and said first bit line; a second switching transistor (34) connected between the second data input-output node of said data-detecting and storing means and said second bit line; data output-controlling means (43, 44, 45) for controlling the external issue of data obtained from the first or second data input-output nodes of said data-detecting and storing means; a pair of data input transistors (41, 42) respectively connected between the first and second data input-output nodes of said data-detecting and storing means and a prescribed potential point; and data input control means (46, 47) for controlling said first and second data input transistors in accordance with the contents of externally supplied writing data.
Claim 8
Dependent Claim
230 words
A semiconductor memory device characterized by comprising: a first bit line (11) connected to memory cells (15) each comprising a nonvolatile transistor (13) and a dummy cell (18) comprising a nonvolatile transistor (16); a second bit line (12) connected to memory cells (15) each comprising a nonvolatile transistor (13) and a dummy cell (18) comprising a nonvolatile transistor (16); first and second high voltage generating means (19 1 , 19 2 ) respectively connected to said first and second bit lines; data-detecting and storing means (20) comprising a flip-flop circuit (27) provided with first and second data input-output nodes (31, 33); a first switching transistor (32) connected between the first data input-output node of said data-detecting and storing means and said first bit line; a second switching transistor (34) connected between the second data input-output node of said data-detecting and storing means and said second bit line; data output-controlling means (43, 44, 45) for controlling the external issue of data obtained from the first or second data input-output nodes of said data-detecting and storing means; a pair of data input transistors (41, 42) respectively connected between the first and second data input-output nodes of said data-detecting and storing means and a prescribed potential point; and data input control means (46, 47) for controlling said first and second data input transistors in accordance with the contents of externally supplied writing data.
References Cited (Backward Citations)
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