Circuit for detecting level of input voltage

Claim 2

A level detection circuit comprising an input terminal supplied with an input voltage, a reference terminal supplied with a reference voltage, first means coupled to said input terminal for converting said input voltage into a first current, second means coupled to said reference terminal for converting said reference voltage into a second current, third means coupled to said first means for producing a third current relative to said first current, fourth means coupled to said second means for producing a fourth current relative to said second current, fifth means coupled to said third and fourth means for combining said third and fourth currents, and an output terminal coupled to said fifth means.

Claim 3

The circuit as claimed in claim 1, wherein said fifth means controls the potential at said output terminal in response to said third and fourth currents.

Claim 4

The circuit as claimed in claim 1, wherein said fifth means comprises a current mirror circuit having an input end connected to said third means and an output end connected to said fourth means, said output terminal being coupled to the output end of said current mirror circuit.

Claim 5

The circuit as claimed in claim 1, wherein said fifth means comprises a current mirror circuit having an input end connected to said fourth means and an output end connected to said third means, said output terminal being coupled to the output end of said current mirror circuit

Claim 6

A comparator comprising first and second input terminals, means for supply an input voltage to one of said first and second input terminals, means for supplying a reference voltage to the other of said first and second input terminals, means coupled to said first input terminal for converting a voltage supplied to said first input terminal into a first current, means coupled to said second input terminal for converting a voltage supplied to said second input terminal into a second current, a first current mirror circuit responding to said first current and producing a third current relative to said first current, a second current mirror circuit responding to said second current and producing a fourth current relative to said second current, a third current mirror circuit having an input end supplied with said third current and an output end supplied with said fourth current, and an output terminal coupled to the output end of said third current mirror circuit

Claim 7

A comparator comprising first and second input terminals, means for supply an input voltage to one of said first and second input terminals, means for supplying a reference voltage to the other of said first and second input terminals, means coupled to said first input terminal for converting a voltage supplied to said first input terminal into a first current, means coupled to said second input terminal for converting a voltage supplied to said second input terminal into a second current, a first current mirror circuit responding to said first current and producing a third current relative to said first current, a second current mirror circuit responding to said second current and producing a fourth current relative to said second current, a third current mirror circuit having an input end supplied with said third current and an output end supplied with said fourth current, and an output terminal coupled to the output end of said third current mirror circuit

Claim 8

The comparator as claimed in claim 5, wherein a power supply voltage is used as said reference voltage.

Claim 9

The comparator as claimed in claim 5, wherein each of said first to third current mirror circuits includes first and second field effect transistors, the gates of said first and second transistors being connected in common, and the gate and drain of said first transistor being connected in common.

Claim 10

A transistor circuit comprising first and second power supply terminals, first and second input terminals, an output terminal, first to fourth node, a first transistor connected between said first power supply terminal and said first node, means for connecting said first input terminal to the control electrode of said first transistor, a first current mirror circuit having an input end coupled to said first node, an output end coupled to said second node and a common end coupled to said second power supply terminal, a second transistor connected between said first power supply terminal and said third node, means for connecting said second input terminal to the control electrode of said second transistor, a second current mirror circuit having an input end coupled to said third node, an output end coupled to said fourth node and a common end coupled to said second power supply terminal, a third current mirror circuit having an input end coupled to said fourth node, an output end coupled to said second node and a common end coupled to said first power supply terminal, means for connecting said output terminal to said second node, means for supplying an input voltage to one of said first and second input terminals, and means for supplying a reference voltage to the other of said first and second input terminals.

Claim 11

A transistor circuit comprising first and second power supply terminals, first and second input terminals, an output terminal, first to fourth node, a first transistor connected between said first power supply terminal and said first node, means for connecting said first input terminal to the control electrode of said first transistor, a first current mirror circuit having an input end coupled to said first node, an output end coupled to said second node and a common end coupled to said second power supply terminal, a second transistor connected between said first power supply terminal and said third node, means for connecting said second input terminal to the control electrode of said second transistor, a second current mirror circuit having an input end coupled to said third node, an output end coupled to said fourth node and a common end coupled to said second power supply terminal, a third current mirror circuit having an input end coupled to said fourth node, an output end coupled to said second node and a common end coupled to said first power supply terminal, means for connecting said output terminal to said second node, means for supplying an input voltage to one of said first and second input terminals, and means for supplying a reference voltage to the other of said first and second input terminals.

Claim 12

The circuit as claimed in claim 8, wherein said other of said first and second input terminal is connected to said second power supply terminal to use a potential at said second power supply terminal as said reference voltage.

Claim 13

The circuit as claimed in claim 8, wherein said first current mirror circuit includes a third transistor connected between said first node and said second power supply terminal and a fourth transistor connected between said second node and said second power supply terminal, the control electrode of said third transistor being connected to said first node and the control electrode of said fourth transistor, said second current mirror circuit including a fifth transistor connected between said third node and said sec. ond power supply terminal and a sixth transistor connected between said fourth node and said second power supply terminal, the control electrode of said fifth transistor being connected to said third node and to the control electrode of said sixth transistor, said third current mirror circuit including a seventh transistor connected between said fourth node and said first power supply terminal and a eighth transistor connected between said second node and said first power supply terminal, and the control electrode of said seventh transistor being connected to said fourth node and to the control electrode of said eighth transistor.

Claim 14

The circuit as claimed in claim 10, wherein said first, second, seventh and eighth transistors are of one conductivity type, and said third, fourth, fifth and sixth transistors are of opposite conductivity type.

Claim 15

A transistor circuit comprising first and second potential terminals, first and second input terminals, first to fourth nodes, a first field effect transistor connected between said first potential terminal and said first node and having a gate connected to said first terminal, a second field effect transistor connected between said first potential terminal and said second node and having a gate connected to said second input terminal, a third field effect transistor connected between said second potential terminal and said first node and having a gate connected to said first node, a fourth field effect transistor connected between said second potential terminal and said third node and having a gate connected to the gate of said third transistor, a fifth field effect transistor connected between said second potential terminal and said second node and having a gate connected to said second node, a sixth field effect transistor connected between said second potential terminal and said fourth node and having a gate connected to the gate of said fifth transistor, a seventh transistor connected between said fourth node and said first potential terminal and having a gate connected to said fourth node, a eighth transistor connected between said third node and said first potential terminal and having a gate connected to the gate of said seventh transistor, means for supplying an input voltage to one of said first and second input terminals, means for supplying a reference voltage to the other of said first and second input terminal, and an output terminal coupled to said third node.

Claim 16

A transistor circuit comprising first and second potential terminals, first and second input terminals, first to fourth nodes, a first field effect transistor connected between said first potential terminal and said first node and having a gate connected to said first terminal, a second field effect transistor connected between said first potential terminal and said second node and having a gate connected to said second input terminal, a third field effect transistor connected between said second potential terminal and said first node and having a gate connected to said first node, a fourth field effect transistor connected between said second potential terminal and said third node and having a gate connected to the gate of said third transistor, a fifth field effect transistor connected between said second potential terminal and said second node and having a gate connected to said second node, a sixth field effect transistor connected between said second potential terminal and said fourth node and having a gate connected to the gate of said fifth transistor, a seventh transistor connected between said fourth node and said first potential terminal and having a gate connected to said fourth node, a eighth transistor connected between said third node and said first potential terminal and having a gate connected to the gate of said seventh transistor, means for supplying an input voltage to one of said first and second input terminals, means for supplying a reference voltage to the other of said first and second input terminal, and an output terminal coupled to said third node.

Claim 17

The circuit as claimed in claim 12, wherein said first, second, seventh and eighth transistors are of one channel type, and said third, fourth, fifth and sixth transistors are of opposite channel type.

Claim 18

A transistor circuit comprising first and second potential terminals, first to fourth nodes, a first series connection circuit of first and second field effect transistors provided between said first potential terminal and said first node, a first input terminal connected to the gate of said first transistor, a second series connection circuit of third and fourth field effect transistors provided between said first potential terminal and said second node, a second input terminal connected to the gate of said third transistor, a fifth field effect transistor connected between said second potential terminal and said first node and having a gate connected to said first node, a sixth field effect transistor connected between said second potential terminal and said third node and having a gate connected to the gate of said fifth transistor, a seventh field effect transistor connected between said second potential terminal and said second node and having a gate connected to said second node, an eighth field effect transistor connected between said second potential terminal and said fourth node and having a gate connected to the gate of said seventh transistor, a third series connection circuit of ninth and tenth field effect transistors provided between said third node and said first potential terminal, means for connecting the gate of said ninth transistor to said first potential terminal, a fourth series connection circuit of eleventh and twelfth field effect transistors provided between said fourth node and said first potential terminal, means for connecting the gate of said eleventh transistor to said fourth node and to the gate of said tenth transistor, an output terminal connected to said third node, a control terminal connected in common to the gates of said second, fourth and twelfth transistors, means for supplying an input voltage to one of said first and second input terminals, means for supplying a reference voltage to the other of said first and second input terminals, and means for supplying a control signal to said control terminal.

Claim 19

A transistor circuit comprising first and second potential terminals, first to fourth nodes, a first series connection circuit of first and second field effect transistors provided between said first potential terminal and said first node, a first input terminal connected to the gate of said first transistor, a second series connection circuit of third and fourth field effect transistors provided between said first potential terminal and said second node, a second input terminal connected to the gate of said third transistor, a fifth field effect transistor connected between said second potential terminal and said first node and having a gate connected to said first node, a sixth field effect transistor connected between said second potential terminal and said third node and having a gate connected to the gate of said fifth transistor, a seventh field effect transistor connected between said second potential terminal and said second node and having a gate connected to said second node, an eighth field effect transistor connected between said second potential terminal and said fourth node and having a gate connected to the gate of said seventh transistor, a third series connection circuit of ninth and tenth field effect transistors provided between said third node and said first potential terminal, means for connecting the gate of said ninth transistor to said first potential terminal, a fourth series connection circuit of eleventh and twelfth field effect transistors provided between said fourth node and said first potential terminal, means for connecting the gate of said eleventh transistor to said fourth node and to the gate of said tenth transistor, an output terminal connected to said third node, a control terminal connected in common to the gates of said second, fourth and twelfth transistors, means for supplying an input voltage to one of said first and second input terminals, means for supplying a reference voltage to the other of said first and second input terminals, and means for supplying a control signal to said control terminal.

Claim 20

The circuit as claimed in claim 14, further comprising a thirteenth field effect transistor connected between said first node and said second potential terminal and a fourteenth field effect connected between said fourth node and said second potential terminal, said control terminal being further connected to the gates of said thirteenth and fourteenth transistors.