Computing system and method providing working set prefetch for level two caches

Claim 2

In a computing system including a processor (100) operative with a three level memory hierarchy comprised of a first level cache (LI; 200), a second level cache (L2; 300) and a main memory (500), with the main memory storing a plurality of sets of information, with each set of information comprised of subsets of information, with the second level cache storing subsets of information, and including usage tables, characterised in that a usage table is operative with the main memory and the second level cache, in which is stored usage information relative to the subset usage of each set of information presently or previously resident in the second level cache, such that when a given set of information is returned main memory from the second level cache, and a given subset thereof is subsequently requested for transfer back to the second level cache, that subset together with only the subsets of the given set which were utilised, during the given set's last residency or last partial residency in the second level cache, are transferred back to the second level cache from the main memory.

Claim 3

A system as claimed in claim 1, wherein the sets and subsets of information are comprised of blocks and lines of information, respectively, and the unit of data requestable by the processor is a double word, a request for a double word, the line containing which is not resident in the first level cache, causes that line to be requested from the second level cache and an entry to be made relative thereto, in the usage table, so that the usage table compiles a history of the line traffic between the two caches but organised in terms of the block organisation of main memory.

Claim 5

4 A method of operating a computer system comprised of at least a processor and a three level memory hierarchy, including a main memory at memory level three in which sets of information are stored at addressable locations, with each set of information being comprised of subsets of information, an L2 cache at memory level two n which a given number of sets of information previously transferred from the main memory are stored, a table operative with the main memory and the second level cache, in which is stored usage information relative to the subset usage of each set of information presently or previously resident in the second level cache, and an L l cache at memory level one in which a given number of subsets of information previously transferred from the L2 cache are stored, the method comprising the steps of: interrogating by the processor, to access a given subset of information, the Ll cache, and if the subset is stored therein, accessing same, and if not; . interrogating by the processor, to access the given subset of information, the L2 cache, and if the subset is stored therein, transferring same to the Ll cache, and if not; interrogating by the processor, to access the given subset of information, the main memory, with the given subset of information, including any other subsets in the same set of information that had previously utilised in a previous residency in the L2 cache, being transferred to the L2 cache; and transferring the given subset of information to the L1 cache from the L2 cache for access by the processor.

Claim 6

4 A method of operating a computer system comprised of at least a processor and a three level memory hierarchy, including a main memory at memory level three in which sets of information are stored at addressable locations, with each set of information being comprised of subsets of information, an L2 cache at memory level two n which a given number of sets of information previously transferred from the main memory are stored, a table operative with the main memory and the second level cache, in which is stored usage information relative to the subset usage of each set of information presently or previously resident in the second level cache, and an L l cache at memory level one in which a given number of subsets of information previously transferred from the L2 cache are stored, the method comprising the steps of: interrogating by the processor, to access a given subset of information, the Ll cache, and if the subset is stored therein, accessing same, and if not; . interrogating by the processor, to access the given subset of information, the L2 cache, and if the subset is stored therein, transferring same to the Ll cache, and if not; interrogating by the processor, to access the given subset of information, the main memory, with the given subset of information, including any other subsets in the same set of information that had previously utilised in a previous residency in the L2 cache, being transferred to the L2 cache; and transferring the given subset of information to the L1 cache from the L2 cache for access by the processor.