Semiconductor memory device

Claim 2

A semiconductor memory device comprising a plurality of bit-line pairs, a plurality of memory cells connected to bit lines constituting respective bit line pairs, a plurality of sense amplifiers each provided to correspond to one bit-line pair and each having a pair of complementary signal terminals connected to the bit lines of the corresponding bit-line pair, a pair of data buses for inputting and outputting data to and from a selected bit-line pair, a data inverting circuit, operatively connected to said pair of data buses, for selectively inverting input/output data in such a way that the charging states of respective memory cells connected to the two bit lines in each bit-line pair become equal for the same input/output data, and a clamp circuit for drawing the potentials of all of the bit lines to a predetermined potential in response to a clear control signal applied when the contents of all of said memory cells are to be cleared.

Claim 3

A semiconductor memory device as set forth in claim 1, wherein each of said memory cells comprises a capacitor for storing data and a MIS transistor for transferring said data between one of said bit lines and said capacitor, whereby said semiconductor memory device constitutes a dynamic random access memory.

Claim 4

A semiconductor memory device as set forth in claim 1, further comprising an output buffer circuit, operatively connected through said data inverting circuit to said pair of data buses, for providing said output data; and a write-in amplifier, operatively connected through said data inverting circuit to said pair of data buses, for receiving said input data.

Claim 5

A semiconductor memory device as set forth in claim 3, wherein said output buffer circuit has two inputs for receiving complementary input signals, said output data being determined in response to said complementary input signals, and said write-in amplifier has two outputs for providing complementary output signals determined in response to said input data.

Claim 6

A semiconductor memory device as set forth in claim 4, wherein said data inverting circuit comprises a switching means for connecting said pair of data buses to said two inputs of said output buffer circuit and to said two outputs of said write-in amplifier, in a cross connection or in a straight connection in accordance with a selection of one of said memory cells.

Claim 7

A semiconductor memory device as set forth in claim 5, further comprising a first group of word lines each intersecting with one of each of said bit line pairs, a second group of word lines each crossing with another one of each of said bit line pairs, and a word decoder operatively receiving address signals and selecting one of said word lies, said switching means comprising a first transistor, a second transistor, a third transistor, and a fourth transistor, said first transistor being connected between one of said data buses and one of said inputs of said output buffer circuit as well as one of said outputs of said write-in amplifier, said second transistor being connected between another of said data buses and another of said inputs of said output buffer circuit as well as another of said outputs of said write-in amplifier, said third transistor being connected between said another of said data buses and said one of said inputs of said output buffer circuit as well as said one of said outputs of said write-in amplifier, and said fourth transistor being connected between said one of said data buses and said another of said inputs of said output buses as well as said another of said outputs of said write-in amplifier, said first and second transistors being simultaneously turned ON in response to said address signals when said first group of word lines is selected, and said third and fourth transistors being simultaneously turned ON in response to said address signals when said second group of word lines is selected.

Claim 8

A semiconductor memory device as set forth in claim 1, wherein said clamp circuit comprises a plurality of clamping transistors each connected between one of said bit lines and the ground, said clamping transistors having gate electrodes operatively receiving said clear control signal when the contents of all of said memory cells are to be cleared.

Claim 9

A semiconductor memory device as set forth in claim 2, further comprising a plurality of word lines each intersecting with one of each of said bit line pairs, said MIS transistor in each memory cell having a gate electrode connected to one of said word lines, and further comprising a word line simultaneous selecting means for simultaneously raising the potentials of all said word lines to be higher than the threshold voltage of said MIS transistor when the contents of all of said memory cells are to be cleared.

Claim 10

A semiconductor memory device as set forth in claim 6, wherein said word decoder comprises a word-line simultaneous selecting means for simultaneously raising the potentials of all of said word lines to be higher than the threshold voltage of said MIS transistor when the contents of all of said memory cells are to be cleared.

Claim 11

A semiconductor memory device as set forth in claim 9, wherein said word decoder comprises an address buffer unit for forming complementary signals of said address signals, and a plurality of NOR gates selectively receiving said complementary signals to select one of said word lines, said word-line simultaneous selecting means comprises means for making all of said complementary signals to low level, whereby all of the outputs of said NOR gates become high level.

Claim 12

A semiconductor memory device as set forth in claim 9, wherein said word decoder comprises an address buffer unit for forming complementary signals of said address signals, and a plurality of NOR gates selectively receiving said complementary signals to select one of said word lines, said word-line simultaneous selecting means comprises means for making all of the outputs of said NOR gates to high level.

Claim 13

A semiconductor memory device as set forth in claim 9, wherein said semiconductor memory device is a dynamic random access memory having a reset interval and an active interval, said word decoder comprises an address buffer unit for forming complementary signals of said address signals, and a plurality of NOR gates selectively receiving said complementary signals to select one of said word lines, said NOR gates each having an output transistor, said word-line simultaneous selecting means comprises means for charging up each gate of said output transistor during said reset interval and for disconnecting each gate of said output transistor from the remaining portion of each of said NOR gates.