Data delay/memory circuit

Claim 2

A data delay/memory circuit comprising: (Fig. 1) a data shift circuit formed of a plurality of clock-controlled data latch circuits (11-17) which are cascade-connected; and means (CG) for supplying said plural data latch circuits (11-17) with clock signals (φ1-φ7) having individual clocking phases and being sequentially generated such that the clocking phase (φ1) for a final stage (17) of said data latch circuits is ahead of that (ϕ7) for an initial stage (I1) of said data latch circuits.

Claim 3

A data delay/memory circuit according to claim 1, characterized in that each of said data latch circuits is of a dynamic type.

Claim 4

A data delay/memory circuit according to claim 2, characterized in that said dynamic data latch circuits include clocked inverters.

Claim 5

A data delay/memory circuit according to claim 1, characterized in that said supplying means (CG) is provided with wirings (W10-W23) for feeding said clock signals (φ1-φ7) which geometrically cross the data transfer direction of said cascade-connected plural data latch circuits.

Claim 6

A data delay/memory circuit comprising: (Figs. 3, 5) a plurality of data delay/memory circuits (DMC1-DMC6) each being formed of a plurality of clock-controlled and cascade-connected data latch circuits (IIA-I7F): means (CG) for supplying said plural data latch circuits (IIA-I7F) with clock signals (φ1-φ7) having individual clocking phases and being sequentially generated such that the clocking phase (01) for a final stage (17) of each of said data latch circuits is ahead of that (φ7) for an initial stage (I1) of each of said data latch circuits; serial/parallel converter means (SPC), coupled to said data delay/memory circuits (DMCl-DMC6) and responsive to serial input data (DX), for supplying respective input terminals of said data latch circuits (IlA-IlF) with data (Dinl-Din6) having individual phases with respect to said serial input data (DX); and parallel/serial converter means (PSC), coupled to said data delay/memory circuits (DMC1-DMC6), for converting data (Doutl-Dout6) delivered from the respective output terminals of said data latch circuits (11A-11F) into serial output data (DY).

Claim 7

A data delay/memory circuit comprising: (Figs. 3, 5) a plurality of data delay/memory circuits (DMC1-DMC6) each being formed of a plurality of clock-controlled and cascade-connected data latch circuits (IIA-I7F): means (CG) for supplying said plural data latch circuits (IIA-I7F) with clock signals (φ1-φ7) having individual clocking phases and being sequentially generated such that the clocking phase (01) for a final stage (17) of each of said data latch circuits is ahead of that (φ7) for an initial stage (I1) of each of said data latch circuits; serial/parallel converter means (SPC), coupled to said data delay/memory circuits (DMCl-DMC6) and responsive to serial input data (DX), for supplying respective input terminals of said data latch circuits (IlA-IlF) with data (Dinl-Din6) having individual phases with respect to said serial input data (DX); and parallel/serial converter means (PSC), coupled to said data delay/memory circuits (DMC1-DMC6), for converting data (Doutl-Dout6) delivered from the respective output terminals of said data latch circuits (11A-11F) into serial output data (DY).

Claim 8

A data delay/memory circuit according to claim 5, characterized in that each of said serial/ parallel converter means (SPC) and said parallel/serial converter means (PSC) is controlled by a.master clock signal and formed of a plurality of cascade-connected data delay circuits (DL10-DL20, DL22-DL32).

Claim 9

A data delay/memory circuit according to claim 5, characterized in that each delay time of the respective signals in said plural data delay/memory circuits (DMC1-DMC6), which are associated with said serial/parallel converter means (SPC) and said parallel/serial converter means (PSC), is set at a prescribed value.