EP0171111A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Process to superpose two positive photoresist layers
Assignee: Nokia Bell NV
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Filing: 1985-07-11
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Granted: —
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Expires: 2005-07-11
Abstract
Abstract This process for superposing two positive photoresist layers on a semiconductor device includes the steps of forming a fluorine containing coating on a portion of the first positive resist layer, baking the thus obtained coated portion between 160°C and 250°C and for 10 to 30 minutes without modifying the properties of the first resist layer, and depositing the second positive resist layer on the thus hardened portion.
Inventors
- 👤 Dirk Maurice Beernaert
- 👤 Rudy Eddy Horre
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-07 00:33
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/20
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
55 words
1) Process for depositing a second positive photoresist layer (10) on a first positive photoresist layer (8, 9) provided on an article, e.g. an electronic chip, characterized in that said process consists in hardening at least a portion of said first layer (8, 9) prior to depositing said second layer (10) directly on said portion.
Claim 2
Dependent Claim
55 words
1) Process for depositing a second positive photoresist layer (10) on a first positive photoresist layer (8, 9) provided on an article, e.g. an electronic chip, characterized in that said process consists in hardening at least a portion of said first layer (8, 9) prior to depositing said second layer (10) directly on said portion.
Claim 3
Dependent Claim
19 words
2) Process according to claim 1, characterized in that said first (8,9) and second (10) resists are substantially identical.
Claim 4
Dependent Claim
21 words
3) Process according to claim 1, characterized in that said hardening is realized by making use of a fluorine containing plasma.
Claim 5
Dependent Claim
32 words
4) Process according to claim 3, characterized in that said fluorine containing plasma is transformed into a fluorine containing coating covering at least said portion of said first resist layer (8, 9).
Claim 6
Dependent Claim
45 words
5) Process according to claim 4, characterized in that said hardening is realized by baking said coated first resist layer (8, 9) at a predetermined temperature ranging from 160 to 250 degrees centigrade and during a predetermined time ran ging from 10 to 30 minutes.
Claim 7
Dependent Claim
37 words
6) Process according to claim 5, characterized in that after said hardening said fluorine containing coating is removed from at least said portion of said first resist layer (8, 9) by means of an oxygen containing plasma.
Claim 8
Dependent Claim
20 words
7) Process according to claim 1, characterized in that said first resist layer (8, 9) is provided with a pattern.
Claim 9
Dependent Claim
26 words
8) Process according to claim 7, characterized in that said hardening is realized after the production of said pattern in said first resist layer (8, 9).
Claim 10
Dependent Claim
19 words
9) Process according to claim 1, characterized in that said second resist layer (10) is provided with a pattern.
Claim 11
Dependent Claim
20 words
10) Semiconductor device, characterized in that it is made in accordance with the process of any of the preceding claims.
Claim 12
Dependent Claim
17 words
11) Semiconductor device according to claim 10, characterized in that it includes at least one MOS transistor.
References Cited (Backward Citations)
No citation records indexed.
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