Patent USRE27172E successfully refreshed from Google Patents.
EP0170977A2
Expired / Lapsed
EP
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Display subsystem
Assignee: Bull HN Information Systems Inc
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Filing: 1985-07-24
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Granted: —
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Expires: 2005-07-24
Abstract
Abstract A display subsystem having a graphics capability includes a bit map memory for storing bits, each bit representing a displayed pixel. A read only memory stores words, each word representative of a pixel of a selected pattern which is used to fill out an area of the display thereby clearly identifying adjacent areas of the display to the operator. The selected patterns are displayed in a REPLACE, an OR or an EXCLUSIVE OR mode of operation.
Inventors
- 👤 Kenneth E. Bruce
- 👤 Thomas Holtey
- 👤 Gary J. Goss
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 21:25
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/14; G06F3/153; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/393
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
264 words
A display subsystem includes apparatus for writing predetermined patterns in an area of a display, said apparatus comprising: read only memory means for storing a plurality of words, each of said plurality of words being representative of a pixel of said predetermined patterns; bit map memory means for storing a plurality of bits, each of said bits being representative of said pixel displayed on said display; microprocessor means coupled to said read only memory means and said bit map memory means for generating a first plurality of address signals for addressing a first memory location of said read only memory means, and generating a second plurality of address signals for addressing a second memory location of said bit map memory means, said microprocessor means further including register means for selecting a mode of operation; and multiplexer means coupled to said read only memory means, said bit map memory means and said microprocessor means and responsive to a plurality of mode signals representative of a REPLACE mode of operation and a plurality of bit signals representative of one of said plurality of words read from said first memory location for generating a write data signal for writing a corresponding bit into said second memory location, said multiplexer means being further responsive to said plurality of mode signals representative of an OR or an EXCLUSIVE OR mode of operation. said plurality of bit signals and a read data signal representative of said corresponding bit read from said second memory location for generating said write data signal for writing said corresponding bit into said second memory location.
Claim 2
Dependent Claim
264 words
A display subsystem includes apparatus for writing predetermined patterns in an area of a display, said apparatus comprising: read only memory means for storing a plurality of words, each of said plurality of words being representative of a pixel of said predetermined patterns; bit map memory means for storing a plurality of bits, each of said bits being representative of said pixel displayed on said display; microprocessor means coupled to said read only memory means and said bit map memory means for generating a first plurality of address signals for addressing a first memory location of said read only memory means, and generating a second plurality of address signals for addressing a second memory location of said bit map memory means, said microprocessor means further including register means for selecting a mode of operation; and multiplexer means coupled to said read only memory means, said bit map memory means and said microprocessor means and responsive to a plurality of mode signals representative of a REPLACE mode of operation and a plurality of bit signals representative of one of said plurality of words read from said first memory location for generating a write data signal for writing a corresponding bit into said second memory location, said multiplexer means being further responsive to said plurality of mode signals representative of an OR or an EXCLUSIVE OR mode of operation. said plurality of bit signals and a read data signal representative of said corresponding bit read from said second memory location for generating said write data signal for writing said corresponding bit into said second memory location.
Claim 3
Dependent Claim
66 words
The apparatus of Claim 1 wherein said microprocessor means comprises: a microprocessor for generating said first plurality of address signals for addressing said first location of said read only memory means, said microprocessor generating said second plurality of address signals for addressing said second location of said bit map memory means, said microprocessor further generating a plurality of data signals indicative of said mode of operation.
Claim 4
Dependent Claim
118 words
The apparatus of Claim 2 wherein said register means for selecting said mode of operation comprises: a register coupled to said microprocessor for storing said plurality of data signals and generating a first mode signal and a second mode signal of said plurality of mode signals wherein said first mode signal in a second state and said second mode signal in a second state indicate said REPLACE mode of operation, said first mode signal in said second state and said second mode signal in a first state indicate said OR mode of operation, and said first mode signal in a first state and said second mode signal in said second state indicate said EXCLUSIVE OR mode of operation.
Claim 5
Dependent Claim
163 words
The apparatus of Claim 3 wherein said multiplexer means comprises: first multiplexer means coupled to said read only memory means and said register means and responsive to said first mode signal in said second state for selecting a first bit signal in a first state of said word of said plurality of words indicating a binary ONE and for selecting said first bit signal in a second state indicating a binary ZERO during said REPLACE or said OR mode of operation; second multiplexer means coupled to said read only memory means and said register and responsive to said first mode signal in said second state for selecting for said OR mode of operation a second bit signal of said word in a first state when said first bit signal is in said second state and selecting said second bit signal in a second state when said first bit signal is in said first state during said REPLACE or said OR mode of operation.
Claim 6
Dependent Claim
95 words
The apparatus of Claim 4 wherein said first multiplexer means is responsive to said first mode signal in said first state for selecting a third bit signal of said word in a first state indicating a binary ONE and for selecting said third bit signal in a second state indicating a binary ZERO during said EXCLUSIVE OR mode of operation; said second multiplexer means is responsive to said first mode signal in said first state for selecting a fourth bit signal of said word in said first state during said EXCLUSIVE OR mode of operation.
Claim 7
Dependent Claim
47 words
The apparatus of Claim 5 wherein saia multiplexer means further comprises: AND gate means coupled to said second multiplexer means and responsive to said second bit signal in said second state for generating a data select signal in a second state during said REPLACE mode of operation.
Claim 8
Dependent Claim
37 words
The apparatus of Claim 6 wherein said AND gate means is coupled to said bit map memory means and is responsive to said second bit signal and said read data signal for generating said data select signal.
Claim 9
Dependent Claim
82 words
The apparatus of Claim 7 wherein said multiplexer means further comprises: exclusive OR means coupled to said first multiplexer means and said AND gate means and responsive to said data select signal in said second state and said first bit signal in said first state for generating a write data signal in a first state. and responsive to said first bit signal in said second state for generating said write data signal in a second state during said REPLACE mode of operation.
Claim 10
Dependent Claim
86 words
The apparatus of Claim 8 wherein said AND gate means is responsive to said second bit signal in said first state when said first bit signal is in said second state, and responsive to said read data signal for generating said data select signal; said AND gate means being further responsive to said second bit signal in said second state when said first bit signal is in said first state for generating said data select signal in said second state during said OR mode of operation.
Claim 11
Dependent Claim
46 words
The apparatus of Claim 9 wherein said exclusive OR means is responsive to said data select signal in said first state and said first bit signal in said second state for generating said write data signal in said first state during said OR mode of operation.
Claim 12
Dependent Claim
46 words
The apparatus of Claim 10 wherein saia exclusive OR means is responsive to said data select signal in said second state and said first bit signal in said first state for generating said write data signal in said first state during said OR mode of operation.
Claim 13
Dependent Claim
77 words
The apparatus of Claim 11 wherein said AND gate means is responsive to said fourth bit signal in said first state and said read data signal in said first state for generating said data select signal in said first state. and responsive to said fourth bit signal in said first state and said read data signal in said second state for generating said data select signal in said first state during said EXCLUSIVE OR mode of operation.
Claim 14
Dependent Claim
47 words
The apparatus of Claim 12 wherein said exclusive OR means is responsive to said third bit signal in said first state and said data select signal in said first state for generating said data write signal in said second state during said EXCLUSIVE OR mode of operation.
Claim 15
Dependent Claim
65 words
The apparatus of Claim 13 wherein said exclusive OR means is responsive to said third bit signal in said first state and said data select signal in said second state, or said third bit signal in said second state and said data select signal in said first state for generating said write data signal in said first state during said EXCLUSIVE OR mode of operation.
Claim 16
Dependent Claim
232 words
A display subsystem includes apparatus for writing predetermined patterns in an area of a display, said apparatus comprising: read only memory means for storing a plurality of words, each of said plurality of words representing a pixel of said predetermined patterns displayed on said display; bit map memory means for storing a plurality of bits, each of said plurality of bits representing said pixel; microprocessor means coupled to said read only memory means and said bit map memory means and having means for selecting said predetermined patterns from said read only memory means for writing said predetermined patterns in said bit map memory means and having means for selecting a REPLACE mode of operation, an OR mode of operation and an EXCLUSIVE OR mode of operation; and multiplexer means coupled to said microprocessor means, said read only memory means and said bit map memory means for receiving signals representative of said predetermined patterns from said read only memory means and writing said signals in said bit map memory means during said REPLACE mode of operation. and said multiplexer means receiving said signals from said read only memory means and receiving first signals representative of said plurality of bits from said bit map memory means, and writing second signals representative of said plurality of bits having a state in accordance with said OR mode of operation or said EXCLUSIVE OR mode of operation.
Claim 17
Dependent Claim
232 words
A display subsystem includes apparatus for writing predetermined patterns in an area of a display, said apparatus comprising: read only memory means for storing a plurality of words, each of said plurality of words representing a pixel of said predetermined patterns displayed on said display; bit map memory means for storing a plurality of bits, each of said plurality of bits representing said pixel; microprocessor means coupled to said read only memory means and said bit map memory means and having means for selecting said predetermined patterns from said read only memory means for writing said predetermined patterns in said bit map memory means and having means for selecting a REPLACE mode of operation, an OR mode of operation and an EXCLUSIVE OR mode of operation; and multiplexer means coupled to said microprocessor means, said read only memory means and said bit map memory means for receiving signals representative of said predetermined patterns from said read only memory means and writing said signals in said bit map memory means during said REPLACE mode of operation. and said multiplexer means receiving said signals from said read only memory means and receiving first signals representative of said plurality of bits from said bit map memory means, and writing second signals representative of said plurality of bits having a state in accordance with said OR mode of operation or said EXCLUSIVE OR mode of operation.
References Cited (Backward Citations)
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