EP0170052A2 — Master slice type semiconductor circuit device

Claim 1

Independent Claim 177 words

A master slice type semiconductor circuit device comprising: at least one memory circuit block having a plurality of input circuits; a plurality of input lines provided to a peripheral portion of said memory circuit block and connected to said input circuits respectively for receiving input signals, said input lines being formed by a first conductive layer; a first conductive line provided to said peripheral portion of said memory circuit block for supplying a first logic level; a second conductive line provided to said peripheral portion of said memory circuit block for supplying a second logic level, said first and second conductive lines being formed by a second conductive layer which is a different layer from said first conductive layer; and contact means for connecting said first or second conductive lines to at least one of said input lines; wherein a potential of at least one of said input signals is clipped to said first or second logic level by said contact means, thereby enabling change of a memory capacity or a function of said memory circuit block.

Claim 2

Dependent Claim 177 words

A master slice type semiconductor circuit device comprising: at least one memory circuit block having a plurality of input circuits; a plurality of input lines provided to a peripheral portion of said memory circuit block and connected to said input circuits respectively for receiving input signals, said input lines being formed by a first conductive layer; a first conductive line provided to said peripheral portion of said memory circuit block for supplying a first logic level; a second conductive line provided to said peripheral portion of said memory circuit block for supplying a second logic level, said first and second conductive lines being formed by a second conductive layer which is a different layer from said first conductive layer; and contact means for connecting said first or second conductive lines to at least one of said input lines; wherein a potential of at least one of said input signals is clipped to said first or second logic level by said contact means, thereby enabling change of a memory capacity or a function of said memory circuit block.

Claim 3

Dependent Claim 24 words

A master slice type semiconductor circuit device as claimed in claim 1, wherein said first and second conductive lines intersect each said input line.

Claim 4

Dependent Claim 89 words

A master slice type semiconductor circuit device as claimed in claim 1, wherein said memory circuit block comprises metal insulator semiconductor (MIS) transistors having gate electrodes, said second conductive layer is the same as a gate electrode layer to form said gate electrodes, and said first and second conductive lines are disposed under said input lines. 4. A master slice type semiconductor circuit device as claimed in claim 1, wherein said first conductive layer is made of an aluminum and said second conductive layer is made of polycrystalline silicon.

Claim 5

Dependent Claim 92 words

A master slice type semiconductor circuit device as claimed in claim 1, wherein said device further comprises: a logic circuit block, having a plurality of first basic cells to form a desired logic circuit, and a plurality of second basic cells, each of which has the same structure as said first basic cells, disposed in said peripheral portion of said memory circuit block tor forming a part of said.input circuit, each of said second basic cells including at least one MIS transistor having a gate electrode as one of said input lines.

Claim 6

Dependent Claim 44 words

A master slice type semiconductor circuit device as claimed in'claim 5, wherein said gate electrode of said MIS transistor in each second basic cell is disposed under said first and second conductive lines, and said gate electrode intersects said first and second conductive lines.

Claim 7

Dependent Claim 31 words

A master slice type semiconductor circuit device as claimed in claim 1, wherein said contact means comprises a contact hole formed between said first conductive layer and said second conductive layer.

Claim 8

Dependent Claim 140 words

A gate array type large-scale integrated circuit device formed by a master slice method comprising: a logic block having a plurality of basic cells arranged in a grid; a memory block having at least one memory circuit; input terminals formed by one conductive layer and provided to peripheral portions of said memory circuit; power source lines provided to said peripheral portions of said memory circuit and formed by a conductive layer different from said one conductive layer of said input terminal; at least one contact hole for clipping between said one conductive layer and said the other conductive layer at a selected input terminal; wherein said selected input terminal clipped by said contact hole is set to a predetermined logic level by said power source lines, thereby enabling change of the memory capacity or a function of said memory block.

Claim 9

Dependent Claim 140 words

A gate array type large-scale integrated circuit device formed by a master slice method comprising: a logic block having a plurality of basic cells arranged in a grid; a memory block having at least one memory circuit; input terminals formed by one conductive layer and provided to peripheral portions of said memory circuit; power source lines provided to said peripheral portions of said memory circuit and formed by a conductive layer different from said one conductive layer of said input terminal; at least one contact hole for clipping between said one conductive layer and said the other conductive layer at a selected input terminal; wherein said selected input terminal clipped by said contact hole is set to a predetermined logic level by said power source lines, thereby enabling change of the memory capacity or a function of said memory block.

Claim 10

Dependent Claim 79 words

A gate array type large-scale integrated circuit device as claimed in claim 8, wherein said memory circuit comprises: a memory cell array constituted by a plurality of memory cells; a sense amplifier group constituted by a plurality of sense amplifiers; a write amplifier group constituted by a plurality of write amplifiers; a word address register group constituted by a plurality of word address registers; a word decoder group constituted by a plurality of word decoders; and a control circuit.

Claim 11

Dependent Claim 27 words

A gate array type large-scale integrated circuit device as claimed in claim 8, wherein said power source line comprises a gate conductive layer under the input terminal.

Claim 12

Dependent Claim 32 words

A gate array type large-scale integrated circuit device as claimed in claim 8, wherein said at least one contact hole is used for connecting said gate conductive layer and said input terminal.

Claim 13

Dependent Claim 20 words

A gate array type large-scale integrated circuit device as claimed in claim 8, wherein said conductive layer comprises aluminum wiring.

Claim 14

Dependent Claim 31 words

A gate array type large-scale integrated circuit device as claimed in claim 8, wherein said aluminum wiring is connected to aluminum wiring of said logic block by using said contact hole.

Claim 15

Dependent Claim 38 words

A gate array type large-scale integrated circuit device as claimed in claim 9, wherein the memory area of said memory cell array is determined by an address signal through said word address register group and word decoder group.

Claim 16

Dependent Claim 30 words

A gate array type large-scale integrated circuit device as claimed in claim 8, wherein said selected input terminal is clipped to said power source line by using said contact hole.

Claim 17

Dependent Claim 131 words

A gate array type large-scale integrated circuit device formed by a master slice method comprising: a logic block having a plurality of basic cells arranged in a grid; a memory block having at least one memory circuit; input basic cell rows provided to peripheral portions of said memory circuit; power source lines provided to said peripheral portions of said memory circuit and tormed by a first conductive layer above said basic cell rows; and at least one contact hole for clipping between said power source line and selected gates of said input basic cell; wherein said selected input basic cell clipped by said contact hole is set to a predetermined logic level by said power source line, thereby enabling change of the memory capacity or a function of said memory block.

Claim 18

Dependent Claim 131 words

A gate array type large-scale integrated circuit device formed by a master slice method comprising: a logic block having a plurality of basic cells arranged in a grid; a memory block having at least one memory circuit; input basic cell rows provided to peripheral portions of said memory circuit; power source lines provided to said peripheral portions of said memory circuit and tormed by a first conductive layer above said basic cell rows; and at least one contact hole for clipping between said power source line and selected gates of said input basic cell; wherein said selected input basic cell clipped by said contact hole is set to a predetermined logic level by said power source line, thereby enabling change of the memory capacity or a function of said memory block.

Claim 19

Dependent Claim 90 words

A gate array type large-scale integrated circuit device as claimed in claim 16, wherein said memory circuit comprises: a memory cell array constituted by a plurality of memory cells; a sense amplifier group constituted by a plurality of sense amplifiers; a write amplifier group constituted by a plurality of write amplifiers; a word address register group constituted by a plurality of word address registers; a word decoder group constituted by a plurality of word decoders; a control circuit; and a basic cell row constituted by a plurality of basic cells.

Claim 20

Dependent Claim 26 words

A gate array type large-scale integrated circuit device as claimed in claim 16, wherein said power source lines comprise aluminum wiring above said basic cell rows.

Claim 21

Dependent Claim 37 words

A gate array type large-scale integrated circuit device as claimed in claim 16, said at least one contact hole is used for connecting said power source lines and a P or N + type substrate contact area.

Claim 22

Dependent Claim 36 words

A gate array type large-scale integrated circuit device as claimed in claim 16, said at least one contact hole is used for connecting said power source lines and P + or N + type diffusion layer.

Claim 23

Dependent Claim 40 words

A gate array type large-scale integrated circuit device as claimed in claim 20, wherein said P or N + type diffusion layer of said selected input basic cell is clipped to said power source line by using said contact hole.

Claim 24

Dependent Claim 118 words

A gate array type large-scale integrated circuit device formed by a master slice method comprising: a logic block having a plurality of basic cells and at least one stacked gate, the basic cells being arranged in a grid; a memory block having at least one memory circuit; power source lines provided to said logic block and formed by first and second conductive layers of aluminum wiring; and at least one contact hole for clipping between said power source line and said stacked gate; wherein said stacked gate clipped by said contact hole is set to a predetermined logic level by said power source line, thereby enabling change of the memory capacity or a function of said memory block.

Claim 25

Dependent Claim 118 words

A gate array type large-scale integrated circuit device formed by a master slice method comprising: a logic block having a plurality of basic cells and at least one stacked gate, the basic cells being arranged in a grid; a memory block having at least one memory circuit; power source lines provided to said logic block and formed by first and second conductive layers of aluminum wiring; and at least one contact hole for clipping between said power source line and said stacked gate; wherein said stacked gate clipped by said contact hole is set to a predetermined logic level by said power source line, thereby enabling change of the memory capacity or a function of said memory block.

Claim 26

Dependent Claim 39 words

A gate array type large-scale integrated circuit device as claimed in claim 22, wherein said memory block further comprises input terminals in peripheral portions thereof to connect said stacked gate and said memory circuit by using said contact hole.

Claim 27

Dependent Claim 39 words

A gate array type large-scale integrated circuit device as claimed in claim 22, wherein said at least one contact hole is used for connecting between said power source line and a P or N + type substrate contact area.

Master slice type semiconductor circuit device

Abstract

Inventors

Bibliographic Details

Claims Analysis

References Cited (Backward Citations)

USPTO Annuity & Maintenance Windows

Assigned Categories & Tags

Assign Category Tag