Multiple phase-splitter TTL output circuit with improved drive characteristics

Claim 2

A multiple phase-splitter TTL output circuit having a signal output (OUT) for delivering binary signals of high or low potential, pulldown transistor means (Q4) for sinking current from the signal output to low potential, a plurality of phase-splitter transistor means (Q2. Q3) having emitters coupled in parallel to the base of the pulldown transistor means (Q4) for controlling the conducting state of the pulldown transistor means, feedback diode means (D2) coupled between the signal output and the collector of a first phase-splitter transistor means (Q2) to accelerate sinking of current from the output to low potential during transition of binary signals at the output from high to low potential, characterized by comprising : a plurality of independent base drive means (Qla, Rla, Qlb. Rlb) a first one (Qla) of said base drive means coupled to the base of the first phase-splitter transistor means (Q2) independent from base drive coupled to the other phase splitter transistor means thereby preventing current hogging of the base drive current to the first phase-splitter transistor means (Q2) by the other phase-splitter transistor means.

Claim 3

The circuit of Claim 1 characterized in that said first base drive means comprises a separate base drive resistor (Rla) coupled in a circuit between high potential and the base of the first phase-splitter transistor means (Q2) for providing independent base drive.

Claim 4

The circuit of Claim 2 characterized in that each base drive means comprises an input transistor (Qla, Qlb) operatively coupled with a phase-splitter transistor means (Q2. Q3). the collector of the input transistor (Qla. Qlb) being coupled to the base of the corresponding phase-splitter transistor means (Q2, Q3), and a base drive resistor (Rla, Rlb) coupled between the base of the input transistor (Qla, Qlb) and high potential.

Claim 5

A multiple phase-splitter TTL output circuit having a signal input (IN), a signal output (OUT), a pulldown transistor element (Q4) for sinking current from the signal output to low potential, a pullup transistor element (Q5. Q6) for sourcing current to the signal output from high potential, a plurality of phase-splitter transistor elements (Q2. Q3) having respective emitters coupled in parallel to the base of the pulldown transistor element (Q4) for controlling the conducting state of the pulldown transistor element, feedback diode means (D2) coupling the signal output to the collector of a first phase-splitter transistor element (Q2) for accelerating sinking of current from the signal output to low potential during transition at the signal output from high to low potential, a second one (Q3) of said phase-splitter transistor elements having its collector coupled to the base of the pullup transistor element (Q6) for controlling the conducting state of the pullup transistor element, and an enable input (OE) coupled to the base of the pullup transistor element (Q5, Q6) and also coupled respectively to the bases of the multiple phase-splitter transistor elements (Q2. Q3) for establishing a high impedance third state at the signal output, characterized by comprising: first and second independent base drive means (Qla, R1a, Qlb. Rlb) operatively coupled respectively to the bases of the first and second phase-splitter transistor elements (Q2. Q3) thereby preventing current hogging of the base drive current to the first phase-splitter transistor element (Q2) by the second phase-splitter transistor element (Q3) and thereby maintaining a high sink current mode through the pulldown transistor element (Q4) during transition from high to low potential at the signal output.

Claim 6

A multiple phase-splitter TTL output circuit having a signal input (IN), a signal output (OUT), a pulldown transistor element (Q4) for sinking current from the signal output to low potential, a pullup transistor element (Q5. Q6) for sourcing current to the signal output from high potential, a plurality of phase-splitter transistor elements (Q2. Q3) having respective emitters coupled in parallel to the base of the pulldown transistor element (Q4) for controlling the conducting state of the pulldown transistor element, feedback diode means (D2) coupling the signal output to the collector of a first phase-splitter transistor element (Q2) for accelerating sinking of current from the signal output to low potential during transition at the signal output from high to low potential, a second one (Q3) of said phase-splitter transistor elements having its collector coupled to the base of the pullup transistor element (Q6) for controlling the conducting state of the pullup transistor element, and an enable input (OE) coupled to the base of the pullup transistor element (Q5, Q6) and also coupled respectively to the bases of the multiple phase-splitter transistor elements (Q2. Q3) for establishing a high impedance third state at the signal output, characterized by comprising: first and second independent base drive means (Qla, R1a, Qlb. Rlb) operatively coupled respectively to the bases of the first and second phase-splitter transistor elements (Q2. Q3) thereby preventing current hogging of the base drive current to the first phase-splitter transistor element (Q2) by the second phase-splitter transistor element (Q3) and thereby maintaining a high sink current mode through the pulldown transistor element (Q4) during transition from high to low potential at the signal output.

Claim 7

The circuit of Claim 4 characterized in that each independent base drive means comprises a base drive resistor (R1a, Rlb) and an input transistor (Qla. Q1b), said base drive resistor coupled between high potential and the base of the input transistor, said input transistor (Qla, Qlb) coupled between a respective phase-splitter transistor element (Q2, Q3) and the signal input (IN) with the emitter of the input transistor coupled to the signal input and the collector of the input transistor coupled to the base of the respective phase-splitter transistor element.

Claim 8

The circuit of Claim 4 characterized in that each of the independent base drive means comprises base drive resistor means (Rla, Rlb) coupled in a circuit between the base of a respective phase-splitter transistor element (Q2, Q3) and high potential, and diode means (D6. D8) coupling the respective first and second base drive means to the enable input (OE).

Claim 9

The circuit of Claim 6 characterized by further comprising an enable diode means (D7) coupled between the base of the pullup transistor element (Q5, Q6) and the enable input (OE), said enable diode means (D7) oriented for passing current in the direction of the enable input (OE).