EP0169332A2
Expired / Lapsed
EP
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High density one device memory
Assignee: International Business Machines Corp
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Filing: 1985-05-23
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Granted: —
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Expires: 2005-05-23
Abstract
Abstract A memory is provided which includes a semiconductor substrate having a diffusion region disposed therein, first, second, third and fourth storage capacitors, first, second, third and fourth switching or transfer devices for coupling the first, second, third and fourth storage capacitors, respectively, to the diffusion region, a common conductor connected to the diffusion region and means for selectively activating the switching devices. In a more specific aspect of this invention, a plurality of groups of the four storage capacitors are arranged so that each of these capacitors is selectively coupled to the common conductor. In another aspect of this invention, the storage capacitors of the plurality of groups are arranged in parallel rows with the common conductor arranged obliquely to the direction of the rows of storage capacitors.
Inventors
- 👤 Roy Edwin Scheuerlein
- 👤 Russell Charles Lange
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 23:22
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/404; G11C11/4063; G11C11/407; G11C11/408; G11C11/409; G11C11/4097; Y; Y10; Y10S; Y10S257/00; Y10S257/911
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
42 words
A memory comprising a semiconductor substrate having a common diffusion region disposed therein, first, second, third and fourth storage capacitors, and first, second, third and fourth switching devices coupling said first, second, third and fourth storage capacitors, respectively, to said diffusion region.
Claim 2
Dependent Claim
42 words
A memory comprising a semiconductor substrate having a common diffusion region disposed therein, first, second, third and fourth storage capacitors, and first, second, third and fourth switching devices coupling said first, second, third and fourth storage capacitors, respectively, to said diffusion region.
Claim 3
Dependent Claim
62 words
A memory as set forth in claim 1 wherein said storage capacitors include storage nodes disposed within said substrate and plates made of a first layer polysilicon and said switching devices are field effect transistors having gate electrodes made of second and third layers of polysilicon and further including a bit/sense line made of a conductive metallic material contacting said diffusion region.
Claim 4
Dependent Claim
31 words
A memory as set forth in claim 1 or 2 wherein said common diffusion region and said storage nodes are N+ diffusion regions and said substrate has a P type conductivity.
Claim 5
Dependent Claim
71 words
A memory as set forth in one of claims 1 to 3 wherein said first and third capacitors and said first and third switching devices are aligned along a first axis through said common diffusion region and said second and fourth capacitors and said second and fourth switching devices are aligned along a second axis through said common diffusion region orthogonal to said first axis thus forming a cross shaped arrangement.
Claim 6
Dependent Claim
50 words
A memory array consisting of groups of memories as set forth in one of the claims 1 to 4 wherein one of the storage capacitors of a first of said groups is disposed adjacent to and between a storage capacitor of a second and of a third group of cells.
Claim 7
Dependent Claim
88 words
A memory array as set forth in claim 5 wherein said diffusion regions and said groups of cells are arranged in a plurality of columns and further including a plurality of bit/sense lines and a plurality of word lines, one of said bit/sense lines being connected to each of the diffusion regions of a respective column of said plurality of columns of diffusion regions and one of said word lines being connected to one of the switching devices of each of said plurality of columns of cell groups.
Claim 8
Dependent Claim
33 words
A memory array as set forth in claim 5 or 6 wherein said bit/sense line is a metallic line and said one word line has a zigzag configuration and is made of polysilicon.
Claim 9
Dependent Claim
71 words
A memory array as set forth in one of the claims 5 to 7 wherein said plurality of word lines includes a first set of word lines and a second set of word lines, said first set of word lines being coupled to two of said four cells of each of said groups and said second set being of word lines being coupled to the remaining two of said four cells.
Claim 10
Dependent Claim
45 words
A memory array as set forth in claim 8 wherein said first set of word lines are polysilicon lines arranged in a first layer over said substrate and said second set of word lines are polysilicon lines arranged in a second layer over said substrate.
Claim 11
Dependent Claim
43 words
A memory array as set forth in claim 9 wherein the lines of said first set of word lines and the lines of said second set of word lines are arranged generally in parallel to each other and orthogonal to said bit/sense lines.
Claim 12
Dependent Claim
38 words
A memory array as set forth in claim 9 or 10 wherein the lines of said first set of word lines are diagonal to the lines of said second set of word lines and to said bit/sense lines.
Claim 13
Dependent Claim
38 words
A memory array as set forth in one of the claims 8 to 11 wherein each of the lines of said second set of word lines includes a plurality of segments and a metallic strap interconnects said segments.
Claim 14
Dependent Claim
35 words
A memory array as set forth in one of the claims 9 to 12 wherein a plate of each of said storage capacitors is a polysilicon plate arranged in a third layer over said substrate.
Claim 15
Dependent Claim
21 words
A memory array as set forth in claim 13 wherein said groups are isolated from each other by a recessed oxide.
References Cited (Backward Citations)
No citation records indexed.
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