Interrupt level sharing circuit

Claim 2

In an interrupt system having an interconnection for an external interrupt signal, a shared interrupt interface circuit for permitting sharing of interrupt levels, characterized in that it comprises: pulse generating means (36, 38, 40) for impressing on said interconnection a pulse transition to a first level from a second level, said interconnection being held at said first level if any such pulse generating means is impressing a first level on said interconnection; interrupt state means (32) having an interrupt state and a noninterrupt state in response to an internal interrupt signal generated by a device requesting an interrupt, said state means causing said pulse generating means to generate said transition to said first level when said state means are in said interrupt state; inhibiting means (44) responsive to a transition to said first level on said interconnection for inhibiting the generation of any subsequent first level signal by said pulse generating means; and reenabling means (50) responsive to a signal indicating an end of interrupt servicing for releasing the inhibiting by said inhibiting means.

Claim 3

A shared interrupt interface circuit according to Claim 1, characterized in that it comprises signal combining means (34) connected to said interrupt state means and said interconnection for preventing said pulse generating means from initiating the generation of said first level signal when a first level signal is present on said interconnection.

Claim 4

A shared interrupt interface circuit according to Claim 1 or 2, wherein said inhibiting means and said reenabling means together comprise a flip-flop (44), said flip-flop being connected to said interconnection and to a first line carrying said end of interrupt servicing signal, said flip-flop being set by said transition to said first level on said interconnection and being cleared by said end of interrupt service signal on said first line, the output of said flip-flop being connected to an enabling input (CLR) of said pulse generating means.

Claim 5

A shared interrupt interface circuit according to Claim 1, 2 or3: characterized in that; in said pulse generating means comprises output means having (40) a first state of said first level, said first state being a voltage state, and a second state of high impedance; and further comprising voltage pull-up means (42)connected to said interconnection for pulling the voltage on said interconnection to said second level when only high impedance output means are connected to said interconnection.

Claim 6

A shared interrupt interface circuit according to anyone of in Claims 1 to 4, characterized in that ie comprises an input port mrans (IO, 46) accessible by an addressable output function of a computer system, said input port receiving a signal from said output function producing said end of interrupt servicing signal.

Claim 7

A shared interrupt interface circuit for a computer system operating with a clock (SYS CLOCK) and an external interrupt line (CARD INT) and having an addressable output function, (IO) said computer system responding to an interrupt when the signal on said external interrupt line (30) transitions from a first level to a second level, comprising: a signal combining gate receiving said interrupt line (30) and an internal interrupt line (CARD INT), the signal on said internal interrupt line changing state when an interrupt is requested; a first flip-flop receiving (36) the output of said signal combining gate and said clock; a pulse generating circuit (38) receiving the output of said first flip-flop and clocked by said clock for producing a negative pulse on said external interrupt line, said pulse generating circuit having an output circuit (40, 42) that pulls said external interrupt line to said first level regardless of the outputs of other similar output circuits connected to said external interrupt line; a second flip-flop (44) receiving the external interrupt line and having an output connected to disabling inputs (CLR) of said first flip-flop and of said pulse generating circuit; and an input port means (IO, 46, 48, 50) accessible by said output function of said computer system, the output of said port means connected to a disabling input of said second flip-flop.

Claim 8

A shared interrupt interface circuit for a computer system operating with a clock (SYS CLOCK) and an external interrupt line (CARD INT) and having an addressable output function, (IO) said computer system responding to an interrupt when the signal on said external interrupt line (30) transitions from a first level to a second level, comprising: a signal combining gate receiving said interrupt line (30) and an internal interrupt line (CARD INT), the signal on said internal interrupt line changing state when an interrupt is requested; a first flip-flop receiving (36) the output of said signal combining gate and said clock; a pulse generating circuit (38) receiving the output of said first flip-flop and clocked by said clock for producing a negative pulse on said external interrupt line, said pulse generating circuit having an output circuit (40, 42) that pulls said external interrupt line to said first level regardless of the outputs of other similar output circuits connected to said external interrupt line; a second flip-flop (44) receiving the external interrupt line and having an output connected to disabling inputs (CLR) of said first flip-flop and of said pulse generating circuit; and an input port means (IO, 46, 48, 50) accessible by said output function of said computer system, the output of said port means connected to a disabling input of said second flip-flop.

Claim 9

A shared interrupt interface circuit according to Claim 6, wherein said output circuit (40, 42) selectively produces a low level voltage signal on said external interrupt line (30) or presents a high impedance to said external interrupt line and further comprises a pull-up resistor (42) connected between said external interrupt line and a positive voltage.