Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
126 words
A high performance, vertical NPN transistor structure formed within an integrated circuit having: an isolated pocket of N type epitaxial layer (12) within a P type monocrystalline silicon substrate (10); a N subcollector region (11); a N + collector reach through (13) which connects said subcollector to a major surface of the structure; a N + emitter region (28) extending from said major surface; a base region including a P intrinsic base region (22) located above said subcollector and below said emitter; a P extrinsic base (29) surrounding both said emitter and intrinsic base regions; characterized in that there is a portion (30) of a lightly doped N intermediate region (23, FIG. 11) extending from said major surface and located between said emitter and extrinsic base.
Claim 2
Dependent Claim
126 words
A high performance, vertical NPN transistor structure formed within an integrated circuit having: an isolated pocket of N type epitaxial layer (12) within a P type monocrystalline silicon substrate (10); a N subcollector region (11); a N + collector reach through (13) which connects said subcollector to a major surface of the structure; a N + emitter region (28) extending from said major surface; a base region including a P intrinsic base region (22) located above said subcollector and below said emitter; a P extrinsic base (29) surrounding both said emitter and intrinsic base regions; characterized in that there is a portion (30) of a lightly doped N intermediate region (23, FIG. 11) extending from said major surface and located between said emitter and extrinsic base.
Claim 3
Dependent Claim
31 words
A transistor as recited in claim 1 wherein there is a remaining portion of said epitaxial layer (12, FIG. 13) between said intrinsic base region (22) and said subcollector region (11).
Claim 4
Dependent Claim
123 words
A high performance vertical NPN transistor having a heavily doped P base contact (16) separated from the emitter opening (26) by an insulating spacer (25) comprising: a heavily doped N emitter region (28); a heavily doped P extrinsic base region (29) formed by out diffusion of P type dopants from said doped polysilicon base contact (16); an intrinsic P base region (22) beneath said heavily doped emitter region and extending into contact with said extrinsic base region; a N type collector region (12, 11) beneath said intrinsic base region; and, a portion (30) of a lightly doped N intermediate region (23, FIG. 11) located beneath said insulating spacer and extending between said heavily doped emitter (28) and said heavily doped extrinsic base (29).
Claim 5
Dependent Claim
123 words
A high performance vertical NPN transistor having a heavily doped P base contact (16) separated from the emitter opening (26) by an insulating spacer (25) comprising: a heavily doped N emitter region (28); a heavily doped P extrinsic base region (29) formed by out diffusion of P type dopants from said doped polysilicon base contact (16); an intrinsic P base region (22) beneath said heavily doped emitter region and extending into contact with said extrinsic base region; a N type collector region (12, 11) beneath said intrinsic base region; and, a portion (30) of a lightly doped N intermediate region (23, FIG. 11) located beneath said insulating spacer and extending between said heavily doped emitter (28) and said heavily doped extrinsic base (29).
Claim 6
Dependent Claim
28 words
A transistor as recited in claim any of above wherein the depth of said intermediate region (23, FIG. 11) is equal to the depth of said emitter (28).
Claim 7
Dependent Claim
25 words
A transistor as recited in claim 4 wherein said portion (30) of said intermediate region (23, FIG. 11) is either ring or square annular shaped.
Claim 8
Dependent Claim
277 words
In a process for fabricating an improved bipolar transistor within an integrated circuit having an isolated region of N type epitaxial layer (12) within a P type monocrystalline silicon substrate (10), a N + subcollector region (11), a N + collector reach through (13) which connects said subcollector to a major surface of the structure, said process further comprising the steps of: a) forming a heavily boron doped polysilicon base contact layer (16) over said isolated region; b) blanket depositing a first insulating layer (18) onto the whole structure; c) forming an opening (21) in both layers (16, 18) to define the intrinsic base of the transistor; d) ion implanting boron ions into said opening (21) to form said intrinsic base (22); e) ion implanting arsenic ions into said opening (21) to form a lightly doped N intermediate region (23) close to the exposed major surface; f) blanket depositing a second insulating layer (24) by chemical Vapor Deposition onto the whole structure; g) reactive ion etching the horizontal portions of said second insulating layer (24), to leave an insulating spacer (25) on the sidewalls of said opening (21) to define the emitter opening (26); h) forming the N doped emitter (28); i) utilizing a heat cycle to drive in the dopants from said intermediate region (23) and from said emitter (28) until the latter reaches the intrinsic base region (22), and to out diffuse and drive in the P dopant from the P polysilicon base contact to form the P extrinsic base (29), but leaving a portion (30) of said intermediate region extending between said emitter and extrinsic base regions and located beneath said insulating spacer (25).
Claim 9
Dependent Claim
277 words
In a process for fabricating an improved bipolar transistor within an integrated circuit having an isolated region of N type epitaxial layer (12) within a P type monocrystalline silicon substrate (10), a N + subcollector region (11), a N + collector reach through (13) which connects said subcollector to a major surface of the structure, said process further comprising the steps of: a) forming a heavily boron doped polysilicon base contact layer (16) over said isolated region; b) blanket depositing a first insulating layer (18) onto the whole structure; c) forming an opening (21) in both layers (16, 18) to define the intrinsic base of the transistor; d) ion implanting boron ions into said opening (21) to form said intrinsic base (22); e) ion implanting arsenic ions into said opening (21) to form a lightly doped N intermediate region (23) close to the exposed major surface; f) blanket depositing a second insulating layer (24) by chemical Vapor Deposition onto the whole structure; g) reactive ion etching the horizontal portions of said second insulating layer (24), to leave an insulating spacer (25) on the sidewalls of said opening (21) to define the emitter opening (26); h) forming the N doped emitter (28); i) utilizing a heat cycle to drive in the dopants from said intermediate region (23) and from said emitter (28) until the latter reaches the intrinsic base region (22), and to out diffuse and drive in the P dopant from the P polysilicon base contact to form the P extrinsic base (29), but leaving a portion (30) of said intermediate region extending between said emitter and extrinsic base regions and located beneath said insulating spacer (25).
Claim 10
Dependent Claim
36 words
In a process as recited in claim 6 wherein said step h) of forming the N + emitter (28) is obtained from out diffusing the N dopant from a N + doped polysilicon emitter contact (27).
Claim 11
Dependent Claim
36 words
In a process as recited in claim 6 wherein said step h) of forming the N + emitter (28) is obtained by implanting arsenic ions at the vicinity of the exposed surface in emitter opening (26).