EP0166642A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Block-divided semiconductor memory device having divided bit lines
Assignee: Fujitsu Ltd
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Filing: 1985-05-30
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Granted: —
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Expires: 2005-05-30
Abstract
Abstract In a semiconductor memory device, memory cells are divided into a plurality of blocks. A plurality of partial bit lines (BL 1, BL 1 , BL 2 , BL 2 , ...) are provided separately for each of the blocks, and a plurality of bus bit lines (BL 0 , BL 0 ) are provided commonly for the respective partial bit lines of each of the blocks. Linked between the partial bit lines (BL,, BL 2 , BL 2 , ...) and the bus bit lines (BL o , BL o ) are transfer gates (Q 1 , Q' 1 , Q 2 , Q' 2' ...). Data of each memory cell is transferred from the respective partial bit lines via the turned ON transfer gates to the respective bus bit lines (BL o , ).
Inventors
- 👤 Yoshihiro Takamae
- 👤 Masao Taguchi
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 19:06
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/4076; G11C11/406; G11C11/408; G11C11/409; G11C11/4096; G11C11/4097
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
176 words
A semiconductor memory device comprising: a memory cell array (1, 2, ..., 1-1, 1-2; 2-1, 2-2; ...) divided into a plurality of blocks; a plurality of partial bit line means (BL 1 , , BL 2 , BL2 ' ...), each provided for one of said plurality of blocks; a plurality of bus bit line means (BL 0 , BL 0 ), each provided commonly for the respective partial bit line means of each of said plurality of blocks; a plurality of data transfer means (Q 1 , Q 1 ', Q 2 ' Q 2 ', ...), each linked between one of said plurality of bus bit line means and one of said plurality of partial bit line means; and selecting means, connected to said plurality of data transfer means, for selecting and turning on at least one of said plurality of data transfer means, so as to transmit data of said memory cell array from the respective partial bit line means via the selected data transfer means to the respective bus bit line means.
Claim 2
Dependent Claim
176 words
A semiconductor memory device comprising: a memory cell array (1, 2, ..., 1-1, 1-2; 2-1, 2-2; ...) divided into a plurality of blocks; a plurality of partial bit line means (BL 1 , , BL 2 , BL2 ' ...), each provided for one of said plurality of blocks; a plurality of bus bit line means (BL 0 , BL 0 ), each provided commonly for the respective partial bit line means of each of said plurality of blocks; a plurality of data transfer means (Q 1 , Q 1 ', Q 2 ' Q 2 ', ...), each linked between one of said plurality of bus bit line means and one of said plurality of partial bit line means; and selecting means, connected to said plurality of data transfer means, for selecting and turning on at least one of said plurality of data transfer means, so as to transmit data of said memory cell array from the respective partial bit line means via the selected data transfer means to the respective bus bit line means.
Claim 3
Dependent Claim
46 words
A device as set forth in claim 1, further comprising a plurality of sense amplifiers (SA 1 , SA 2 , ...), each connected to one of said plurality of partial bit line means, for amplifying the potential at said plurality of partial bit line means.
Claim 4
Dependent Claim
46 words
A device as set forth in claim 2, wherein said plurality of partial bit line means comprises a pair of partial bit lines (BL 1 , BLl , BL 2 , , ...) of a folded type connected to one of said plurality of sense amplifiers.
Claim 5
Dependent Claim
49 words
A device as set forth in claim 2, wherein said plurality of partial bit line means comprises a pair of partial bit lines (BL 1 , BL , , BL 2 ' BL 2 , ...) of an open type connected to one of said plurality of sense amplifiers.
Claim 6
Dependent Claim
55 words
A device as set forth in claim 1, further comprising: common data bus means (DB, DB); and selecting means (CD), linked between said plurality of bus bit line means and said common data bus means, for selecting one of said plurality of bus bit line means and connecting it to said common data bus means.
Claim 7
Dependent Claim
21 words
A device as set forth in claim 2, where each of said plurality of sense amplifiers incorporates an active restore circuit.
Claim 8
Dependent Claim
45 words
A device as set forth in claim 6, further comprising refreshing means, connected to said memory cell array, for transmitting data of each block of said memory cell array to the respective partial bit line means, without turning on said plurality of data transfer means.
Claim 9
Dependent Claim
55 words
A device as set forth in claim 6, further comprising refreshing means, connected to said memory cell array and said plurality of data transfer means, for transmitting data of each block of said memory cell array to the respective partial bit line means, with turning on only one of said plurality of data transfer means.
Claim 10
Dependent Claim
40 words
A device as set forth in claim 1, further comprising active restore circuits (AR), each connected to one of said plurality of bus bit line means, for pulling up the higher potential at said plurality of partial bit one means.
Claim 11
Dependent Claim
45 words
A device as set forth in claim 9, further comprising refreshing means, connected to said memory cell array, for transmitting data of each block of said memory cell array to the respective partial bit line means, without turning on said plurality of data transfer means.
Claim 12
Dependent Claim
54 words
A device as set forth in claim 9, further comprising refreshing means, connected to said memory cell array and said plurality of data transfer means, for transmitting data of each block of said memory cell array to the respective partial bit line means, turning on only one of said plurality of data transfer means.
References Cited (Backward Citations)
No citation records indexed.
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