Digital data reproducing system

Claim 2

A digital data reproducing system comprising: a first clock generation means(2)for producing a first clock of a frequency larger than f Hz when the transmission rate of an input digital information signal is represented by f b.p.s.; means (1) for quantizing said input digital information signal in synchronism with said first clock; means(3)for equalizing the waveform of the quantized signal; means(4)for carrying out phase interpolation computation with respect to an output of said waveform equalizing means; means (7) for generating a second clock necessary for decoding an output of said phase interpolation computing means to obtain a data string; means (5) for detecting a phase difference between an ideal sampling phase and the phase of the first clock from the output of said waveform equalizing means; and interpolation-and-clock control means(6)for transmitting phase interpolation information to said phase interpolation means(4) according to an output of said phase difference detection means and transmitting information for generating the second clock to said second clock generating means (7).

Claim 3

The digital data reproducing system according to claim 1, wherein the frequency of said first clock is 2 f Hz or more.

Claim 4

A digital data reproducing system according to claim 1, wherein said waveform equalizing means (3) is a digital filter.

Claim 5

A digital data reproducing system according to claim 1. 2 or 3, wherein said waveform equalizing means (3) is provided with a circuit for offsetting a dc component.

Claim 6

A digital data reproducing system according to claim 3, wherein said waveform equalizing means is a transversal filter (35) comprising multipliers (11-13), adders (14-17) and de lay circuit.(18-25).

Claim 7

A digital data reproducing system according to claim 5, wherein said delay circuits (11-25) select a delay time by switches (26-30).

Claim 8

A- digital data reproducing system according to claim 5 or 6, wherein said delay circuits (18-25) are each capable of switching between a one clock delay and a two clock delay.

Claim 9

A digital data reproducing system according to claim 5 or 6, wherein a delay time of an individual one of said delay circuits (18-25) is controlled.

Claim 10

A digital data reproducing system according to claim 5 or 6, wherein the delay times of all of said delay circuits are uniformly controlled.

Claim 11

A digital data reproducing system according to any one of the preceding claims, wherein said phase interpolation computation means (4) comprises a digital filter (41) and means (42) for storing a plurality of sets of tap coefficients of said digital filter.

Claim 12

A digital data reproducing system according to claim 10, wherein said phase interpolation computation means (4) comprises a first multiplier (M) given a quantized input signal string, a delay circuit (L) to delay said input signal string by one clock, a second multiplier (M) given an output of said delay circuit (L), and an adding circuit (40) for adding the outputs of said first and second multipliers.

Claim 13

A digital data reproducing system according to claim 10, wherein said phase interpolation means (4) comprises an adding circuit which gives one of two adjacent signals of said input signal string to said first multiplier having a factor of 1 or 1/2 and which gives the other of said two adjacent signals to said second multiplier having a factor 1, 1/2 or 0 so as to add the outputs of said first and second multipliers, said factors of said first and second multipliers being selected by an output from said control circuit.

Claim 14

A digital dat a reprocucing system according to any one of the preceding claims, wherein said phase difference detection means (5) detects a phase difference from said first clock according to the magnitude relation between two signals in a bit sync signal. 14 . A digital data reproducing system according to claim 13 , wherein said phase difference detection means (5) comprises a multiplier circuit to multiply signs of two adjacent signals in said bit sync signal of the input signal string, a first absolute value circuit(62)for obtaining the absolute values of said two signals, a second absolute value circuit(63) for obtaining the absolute value of a difference between the absolute values of said two signals, a selecting circuit (68) to select a smaller absolute value of the absolute values of said two signals, a first comparator circuit (67) to compare magnitudes of 1/4 of the output of said second absolute circuit(63)with the output of said selecting circuit (68), and a second comparator circuit(66)to compare magnitudes of the output of said second absolute value circuit(63) with 1/2 of the output of said selecting circuit(68), so. that the output of said multiplying circuit, the outputs of said first and second comparator circuits, and the magnitude information of said first comparator circuit are outputted to said interpolation-and-clock control circuit.

Claim 15

A digital data reproducing system according to any one of claims 1 to 12, wherein said phase difference detection means (5) detects a phase difference from said first clock from a byte sync signal.