Silicon-on-insulator transistors

Claim 1

A method of fabricating an integrated semiconductor structure, which contains a substrate with subsequently provided semiconductor or insulation layers with at least two such structures being bonded together, characterized by depositing an epitaxial semiconductor layer (22) on a first side of a first semiconductor substrate (20) ; forming a silicon oxide layer of predetermined thickness on said epitaxial layer; bonding the surface of the resultant structure to a second semiconductor substrate at a predetermined temperature in an oxidizing atmosphere using said silicon oxide layer as a bonding material, thereby forming a bonded structure (Fig. 3); and removing said first substrate from said bonded structure to expose a major surface of said epitaxial layer (Fig. 4).

Claim 2

A method of fabricating an integrated semiconductor structure, which contains a substrate with subsequently provided semiconductor or insulation layers with at least two such structures being bonded together, characterized by depositing an epitaxial semiconductor layer (22) on a first side of a first semiconductor substrate (20) ; forming a silicon oxide layer of predetermined thickness on said epitaxial layer; bonding the surface of the resultant structure to a second semiconductor substrate at a predetermined temperature in an oxidizing atmosphere using said silicon oxide layer as a bonding material, thereby forming a bonded structure (Fig. 3); and removing said first substrate from said bonded structure to expose a major surface of said epitaxial layer (Fig. 4).

Claim 3

A method of fabricating an integrated semiconductor structure, which contains a substrate with subsequently provided semiconductor or insulation layers with at least two such structures being bonded together, characterized by depositing an epitaxial semiconductor layer (22) on a first semiconductor substrate (20) of a conductivity type opposite to that of said epitaxial layer; forming a silicon oxide layer (26) of a predetermined thickness on a second semiconductor substrate (24); bonding said second semiconductor substrate on said epitaxial layer of said first semiconductor substrate at a predetermined temperature in an oxidizing atmosphere using said silicon dioxide layer (26) as the bonding material, thereby forming a bonded structure; removing said first substrate (20) from said bonded structure to expose a major surface of said epitaxial layer (22); forming a masking layer (30) on said epitaxial layer (22); patterning said masking (30) layer to cover preselected active device regions; removing portions of said epitaxial layers (22) exposed by said patterned masking layer (30); forming a field oxide (38) on areas of said epitaxial layer other than said active device regions; removing said masking layer (30); forming a gate oxide (42) and gate electrode (50) over a predetermined portion of said epitaxial layer; defining and forming epitaxial source and drain regions (60, 62) of a conductivity type opposite to the conductivity type in said epitaxial layer; and defining and forming source and drain regions (64, 66) in regions of said second semiconductor substrate (24) adjacent and on either side of one of said epitaxial source and drain regions (60, 62), said source and drain regions (64, 66) having a conductivity type opposite to the conductivity type of said second substrate (24).

Claim 4

A method of fabricating an integrated semiconductor structure, which contains a substrate with subsequently provided semiconductor or insulation layers with at least two such structures being bonded together, characterized by depositing an epitaxial semiconductor layer (22) on a first semiconductor substrate (20) of a conductivity type opposite to that of said epitaxial layer; forming a silicon oxide layer (26) of a predetermined thickness on a second semiconductor substrate (24); bonding said second semiconductor substrate on said epitaxial layer of said first semiconductor substrate at a predetermined temperature in an oxidizing atmosphere using said silicon dioxide layer (26) as the bonding material, thereby forming a bonded structure; removing said first substrate (20) from said bonded structure to expose a major surface of said epitaxial layer (22); forming a masking layer (30) on said epitaxial layer (22); patterning said masking (30) layer to cover preselected active device regions; removing portions of said epitaxial layers (22) exposed by said patterned masking layer (30); forming a field oxide (38) on areas of said epitaxial layer other than said active device regions; removing said masking layer (30); forming a gate oxide (42) and gate electrode (50) over a predetermined portion of said epitaxial layer; defining and forming epitaxial source and drain regions (60, 62) of a conductivity type opposite to the conductivity type in said epitaxial layer; and defining and forming source and drain regions (64, 66) in regions of said second semiconductor substrate (24) adjacent and on either side of one of said epitaxial source and drain regions (60, 62), said source and drain regions (64, 66) having a conductivity type opposite to the conductivity type of said second substrate (24).

Claim 6

The method according to one of the preceding claims, wherein said epitaxial layer and said first substrate have opposite conductivity tpyes.

Claim 7

The method according to one of the preceding claims, wherein said epitaxial layer is of n-type conductivity, said epitaxial layer has a doping concentration below 1 x 10 18 /cm 3 , and said first semiconductor substrate has a doping concentration greater than 6 x 10 /cm .

Claim 8

The method according to one of the preceding claims, wherein said removing step comprises etching with hydrofluoric-nitric-acetic-acid-composition.

Claim 9

The method according to one of the preceding claims, characterized by the further steps of removing said epitaxial layer (22) in selected areas to form active device regions of said epitaxial layer; forming a field oxide (38) on areas of said epitaxial layer other than said active device regions; forming a gate oxide (42, 36) on areas of said epitaxial layer (32) over said active device regions; forming a conductive gate electrode (50) over a predetermined portion of said gate oxide; defining and forming SOI source and drain regions (60, 62) in said epitaxial layer (32) on either side of said gate electrode (50), said SOI regions having a conductivity type the opposite of said epitaxial layer; and defining and forming bulk source and drain regions (64, 66) in portions of said second substrate (24) on either side of at least one of said SOI source and drain regions (60, 62), said bulk regions having a conductivity type opposite the conductivity type of said second substrate (24).

Claim 10

The method according to one of the preceding claims, wherein said epitaxial layer and said second substrate have the same conductivity type.

Claim 11

The method of fabricating a semiconductor structure according to one of claims 1 to 7, wherein said epitaxial layer and said second substrate have opposite conductivity types so said semiconductor structure is of the type of a CMOS-structure.